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divider1
- FPGA 除法器程序-FPGA divider procedures
divider
- 流水型除法器，经过FPGA平台验证。宽度可以任意修改，提供计算完毕信号。-Water-type divider, after a FPGA platform validation. Width can be modified to provide the calculation is completed the signal.
divider
- 16位定点无符号数除法器，除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成-Unsigned 16-bit fixed-point divider, divisor, dividend by 16-bit integer and 16 fractional bits, commercial 32-bit integer and 16 by the decimal form, the remainder from 32 fractional bits
实例模块
- 各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench
div16d8
- 16位除以8位除法器，Verilog HDL语言-16 divided by 8 divider, Verilog HDL language
xunfachufaqi
- 从原理到实现的循环除法器的Verilog代码-Circular divider from the principle to the implementation of the Verilog code
divider.c
- 改良型除法器，用来模拟硬件VLSI除法器的工作步骤，是设计硬件的前序步骤-improved divider
Division-of-digital-tube-display
- 除法器数码管显示，FPGA的verilog代码-Division of digital tube display