搜索资源列表
asynfifo
- 异步FIFO模块： module asynfifo(rst,iclk,oclk,din,wren,rden,dout,full,empty) 异步FIFO的tenchbench： module tb_asynfifo
FIFO
- 一个异步的FIFO的VERILOG程序,有测试程序
CliffordECummingsFIFO
- 超值奉献，Clifford E. Cummings FIFO关于异步FIFO的两篇文章，同时附有中文解说，主要讲解异步FIFO的实现难点---空满标志的产生，以及读写地址的产生
FIFO
- 异步FIFO国外经典教程，包含两篇重量级文献 -Asynchronous FIFO foreign classic tutorials, including two heavyweight literature
yibu_FIFO_design
- 异步FIFO实例，精通verilog hdl中的例子，供大家学习-Asynchronous FIFO instance, in the example verilog hdl proficiency for all learning
fifo
- 基于verilog的异步fifo设计，仿真效果良好-asynchronous fifo based on zhe verilog language
FIFO
- 通用异步FIFO设计的verilog代码，来自于opencore-Universal Asynchronous FIFO Verilog design code, from opencore
asyn_fifo
- verilog编写的异步fifo源代码，asyn_fifo.v为顶层，调用其他四个文件-asynchronous fifo prepared Verilog source code, asyn_fifo.v for top-level, call the other four documents
clk
- 通过一个主时钟信号完成异步FIFO读写时钟信号的产生。编译通过实现功能。-Through a master clock signal the completion of asynchronous FIFO read and write clock signal generation. Compiler through the implementation function.
asynFifo
- 异步fifo在IC设计中，非常重要；是异步时钟域同步方法-Asynchronous fifo in IC design, is very important are asynchronous clock domain synchronization
FIFO
- 异步fifo,希望能给大家带来帮助-异步fifo
synchronousfifo
- 采用SystemC语言编写的异步FIFO,非常适合初学SystemC语言的人作为例子练习。-SystemC language using asynchronous FIFO, SystemC is suitable for beginners to practice the language of the people as an example.
fifo12_12
- 异步fifo.能够实现异步缓冲数据，希望大家能够有帮助-Synchronous fifo, to achieve synchronization of the buffer, the hope that useful
fifo16
- 异步的FIFO。带TESTbenchi。希望对大家有帮助啊-Asynchronous FIFO. With TESTbenchi. I hope to have everyone help ah
fifo16_16
- 异步的fifo,写时钟和读时钟相互独立，能够对数据进行缓存处理。希望对大家有用-Asynchronous fifo, write clock and the read clock independent of each other, capable of processing the data cache. I hope useful
Chapter-9
- 9.1 异步FIFO设计实例 9.2 DDR SDRAM Controller设计实例-9.1 Asynchronous FIFO design example 9.2 DDR SDRAM Controller Design Example
Asynchronous-FIFO-
- 异步FIFO是一种先进先出电路，可以有效解决异步时钟之间的数据传递。通过分析异步FIFO设计中的难点，以降低电路中亚稳态出现的概率为主要目的，大大提高工作频率和资源利用率。-Asynchronous FIFO is an advanced circuit that can effectively solve the data transfer between asynchronous clock. Through the analysis of the difficulties in async