搜索资源列表
0809
- 0809控制器程序 VHDL编写的 仅供参考-0809 controller procedures prepared by the VHDL is for reference only
washing
- 洗衣机控制器 做课程设计的同学可以下了看看 用vhdl语言做的 -washing machine controller design courses so students can see where the use of the VHDL language
verilog_vga
- 用verilog HDL 语言写的在显示器上显示图案的源程序-with Verilog HDL language written on display in the pattern of the source
easylight
- easydetect程序，是交通灯的verilog实现-easydetect process, the traffic lights to achieve verilog
rs-codec(255-223)
- 这是rs（255，223）编码的verilog源程序。里面有：encode、decode、test－bench等文件。-This is rs (255,223) verilog source coding. Inside : encode, decode, test-bench and other documents.
rs-codec-8-4
- encode.v The encoder syndrome.v Syndrome generator in decoder berlekamp.v Berlekamp algorithm in decoder chien-search.v Chien search and Forney algorithm in decoder decode.v The top module of the decoder inverse.v Computes multiplic
pwm_VerilogHDLV1.1
- 本软件在CPLD上实现数字PWM控制，用Verilog HDL语言编写，在MAX ＰＬＵＳ ＩＩ调试成功，可用-the software on the CPLD digital PWM control, using Verilog HDL language, MAX PLUS II in debugging success can be
ver6.0
- windowsxp/2000下驱动程序开发软件winddriver6.0-windowsxp/2000 under driver development software winddriver6.0
Chapter7Sample
- Chapter6Sample,FPGA嵌入式开发书籍的源码，其中含有USB控制器的设计 VHDL语言开发-Chapter6Sample, FPGA embedded development books source code, USB controller contains the VHDL Design Development
mvbc3_ise6_bak
- MVBC VHDL代码．．实现多功能车辆总线的通信-MVBC VHDL code. . Multi-purpose vehicle bus communication
async_transmitter
- 用verilog实现rs232通信async_transmitter.v-with verilog achieve rs232 communications async_transmitter.v
async_receiver
- 用verilog实现rs232 receiveri -with verilog achieve rs232 receiveri
mt48lc4m32b2
- mt48lc4m32b2.v 是128M sdram 中典型设计。。可以借鉴。-mt48lc4m32b2.v 128M sdram is typical design. . Be used.
SRAM_2
- FPGA的SDRAM控制器源程序 FPGA的SDRAM控制器源程序-FPGA SDRAM controller source FPGA SDRAM controller source
fifo_ver_131
- fifo verilog hdl 源程序-fifo verilog hdl source
gold_code_ver_217
- gold_code_ver_217 源程序-gold_code_ver_217 source
DE2_Top
- 一个经过DE2板验证的数字移相信号发生器的HDL原代码!曾经能够获奖的,工程设计的好东西!
crc
- 循环冗余校验，crc_16,主要运用在数字通信系统。用verilog HDL编写
Viterbi
- 卷积码（2，1，6），完整的工程文件，已经调试通过
Xilinxopensourcecode
- xilinx公司的开放的源码，很有参考价值，其中有ddl，fifo控制等。