Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model -Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * M

实现（2，1，7）卷积编码以及相应的viterbi译码-(2,1,7) convolutional code and the corresponding Viterbi decoding