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X-HDL3.2.52
- VHDL与VerilogHDL语言之间相互转换
VerilogHDL
- VerilogHDL的基本知识，初学者可以通过此来学习这门语言，能够很好的透过实例来理解该语言的功能-VerilogHDL the basic knowledge, beginners can learn from this to the language, can be a very good example to understand through the language features
Chapter1-5
- 第一章到第五章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
ddr_contrl
- DDR controller source code and test bench in VerilogHDL. It is very useful to develop DDR project.-DDR controller source code and test bench in VerilogHDL.
MANCHESTER_DECODER
- 射频识别防碰撞算法，用veriloghdl编写。-RFID anti-collision algorithm
lfsr
- 用VerilogHDL编写的lfsr移位寄存器，可以综合。-Lfsr prepared with VerilogHDL shift register, can be summarized.
spi_verilog
- spi接口的verilogHDL编码，用于fpga与单片机的spi总线通讯-spi interface verilogHDL coding
uart
- 基于verilogHDL实现的UART收发，带FIFO缓存。-UART transceiver, with a FIFO buffer.
IEEE_Verilog_2001
- IEEE 1364-2001 VerilogHDL IEEE 1364-2001 VerilogHDL
Reset
- 基于verilogHDL的异步复位，同步释放电路模块文件-Asynchronous reset, synchronous release circuit
ADconversion
- Veriloghdl 代码使用ADC0809来进行ad转换，使用verilog hdl程序来进行ad转化-Veriloghdl ad code uses ADC0809 to convert, using the verilog hdl program to ad conversion
APB_Servo_code_final
- test code by verilogHDL. SERVO MOTER operation code at FPGA. AHB and APB BUS Architecture.