搜索资源列表
usb_funct
- USB接口的VHDL源码，支持Verilog HDL程序-USB VHDL source code, supports Verilog HDL procedures
USBverilog
- verilog USB程序，经过实践调试，并且都能成功实现-verilog USB procedures, debugging practice, and can be successfully achieved
usb
- Altera usb example verilog file.
FPGA_Project
- USB 2.0的数据传输verilog程序，采用的是slave状态机实现其功能。其中包括读、写功能 -USB 2.0 data transfer verilog program, using the slave state machine functionality. Including reading and writing functions