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7seg
- 七段数码显示程序 VHDL 开发环境为Xilinx 的集成开发工具ISE-VHDL digital display program development environment for Xilinx ISE Integrated Development Tools
sanfenpin
- verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in
CSC_XAPP931_pdf
- This document is Xilinx`s Color Space Conversion Applcation Note. This CSC is a RGB to YCrCb Conversion.
ise-10
- VHDL Xilinx ISE 10 Tutorial
Xilinx-ISE-10.1-Quick-Start-Tutorial
- VHDL Xilinx ISE 10.1 Quick Start Tutorial
Xilinx-ISE-WebPACK-VHDL-Tutorial
- Xilinx ISE WebPACK VHDL Tutorial
13.Anvyl_PmodAD1_Demo
- 用VHDL写的AD程序，使用与xilinx开发板。-Written using VHDL AD process, use and xilinx development board.
TechAss-2006
- un controller pi par le langage VHDL xilinx ise design 13.2
SPI-Core_nguyen
- SPI Master Core HDL: VHDL 93 Compatibility: all FPGAs, CPLDs parameterization: - variable data width - Phase/polarity configurable - selectable buffer depth - serial clock devision due to system clock package usage: IEEE
BH_Shi_jizhi_Out
- FPGA开发 VHDL语言 常用进制转换 基于Xilinx开发平台 ISE软件-VHDL language commonly used FPGA development hexadecimal conversion based on Xilinx ISE software development platform
DSSS
- 用VHDL实现基于Xilinx的FPGA上的直接序列扩频通信，并且附带了matlab仿真程序。-VHDL implementation based on direct sequence spread spectrum communication on Xilinx' s FPGA, and comes with matlab simulation program.