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MotorControl
- this the stepper motor contro lcode on xilinx spartan fpgas enjoy the cod e nd keep helpin each other-this is the stepper motor contro lcode on xilinx spartan fpgas enjoy the cod e nd keep helpin each other
sanfenpin
- verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in
CSC_XAPP931_pdf
- This document is Xilinx`s Color Space Conversion Applcation Note. This CSC is a RGB to YCrCb Conversion.
ofdm_baseband_design_basedon_fpga
- 基于Xilinx FPGA的OFDM通信系统基带设计一书的源代码 -this is source code from a book
clk_gen
- this is a clock generator program by using concurrent language verilog hdl with xilinx ise.
New-WinRAR-archive
- This program is of 8 bit full adder on xilinx also tested on cadence tool
New-WinRAR-archive
- This file for 4 bit up down counter tested on xilinx and cadence-This is file for 4 bit up down counter tested on xilinx and cadence
singleTcpu
- 单周期cpu设计，基于xilinx ISE环境设计，使用MIPS语言-Single cycle, the CPU is designed, based on xilinx ISE environment design, the use of MIPS language
nexys4-ddr_sw_demo
- The Nexys4 DDR board is a complete, ready-to-use digital circuit development platform based on the latest Artix-7™ Field Programmable Gate Array (FPGA) Xilinx® . With its large, high-capacity FPGA (Xilinx part number XC7A100T-1CSG324C)