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rs-codec-8-4
- encode.v The encoder syndrome.v Syndrome generator in decoder berlekamp.v Berlekamp algorithm in decoder chien-search.v Chien search and Forney algorithm in decoder decode.v The top module of the decoder inverse.v Computes multiplic
async_transmitter
- 用verilog实现rs232通信async_transmitter.v-with verilog achieve rs232 communications async_transmitter.v
async_receiver
- 用verilog实现rs232 receiveri -with verilog achieve rs232 receiveri
Viterbi
- 卷积码（2，1，6），完整的工程文件，已经调试通过
reed_solomon
- rs的译码器，rs译码是一个比较复杂的过程
CRC32_D8
- crc32编码的代码
RS_5_3_GF256_5
- Redd-Solomon (5,3) Code，和前面一个有所不同
VB219
- （2，1，9）VB译码器Verilog代码
acs
- 卷积码的解码所用到的加比选模块 很有用 可直接引用
voice-cpld
- 在CPLD内实现声调和时间的控制，在LATTICE的ISPLEVER6.1下编译通过。可以修改定时时间进行声调的修改
QuickSOPC-1C6
- VHDL实验版。供大开发的所有程序。家学习交流！-VHDL experimental version. For the development of all programs. Home Learning Exchange!
fen_zu_interlacing
- 一个简单的交织实现程序，可以自己看看，具体功能很简单，如果看不懂的话可以留言哦，欢迎交流哦-Interwoven to achieve a simple procedure, can take a look at the specific function is very simple, If you do not know if can post Oh, welcomed the exchange of Oh
i2c_top
- This a code for Verilog for I2C-This is a code for Verilog for I2C
4
- lease read your package and describe it at least 40 bytes. System will automatically delete the directory of debug and release, so please do not put files on these two directory
signal
- 产生编码解码时使用的clk_1以及频率为它31倍的clk_31信号。 //产生M序列的发送信号indata(随机),并且将接收到的解码信号（decode）进行比较。 //发送的头10个信号为1，第11个为0，在解码的开始时期进行同步判断时用到。-Have used codec clk_1 as well as the frequency of 31 times it clk_31 signal.// Generate the M sequence signal indata (rando
decode
- //接收端的解码模块（可综合） //在信号接收的刚开始发送端发送的是10个1信号， //即10个+M序列，所以我们在开始时每接收到一个信号做一次累加运算 //当出现正的高峰时则认为达到同步，进入同步解调过程（mainbody）。 //也就是从此每进入一个信号就进行相应的相乘相加， //在解接收到31个信号后进行一次判断，大于0认为接收到1，小于0认为接收到0。-//Receiver decoder module (which can be integrated)// at t
vga_demo.v.tar
- vga controller made for basic students projects in fpga vga controller made for basic students projects in fpga -vga controller made for basic students projects in fpga vga controller made for basic students projects in fpga vga controller
alu.v.tar
- alu source code for begginer students of electrical ingenierings, adaptable for different needs according to the subject request s
calculadora.v.tar
- basic special calculator for begginer students of electrical engineerings
contadorcito.v.tar
- basic begginers up-down 1 bit couter