搜索资源列表
8051core-Verilog
- verilog 描述8051core参考学习用
asynfifo
- 异步FIFO模块： module asynfifo(rst,iclk,oclk,din,wren,rden,dout,full,empty) 异步FIFO的tenchbench： module tb_asynfifo
dfifo
- verilog，异步一进一出的例子，空满的标志。
FIFO
- fifo.v verilog实现的先进先出存储器
fifo_1
- 这是一个先进先出FIFO存储器的设计源码
AD7864
- 这是对上次AD7864采样程序的改进，增加了FIFO的编程，功能比上次源码更加完善！-This sourse is modified and I have added the program of FIFO,so its function is better then privious one.I hope it is helpful for you!
FIFO
- 通用异步FIFO设计的verilog代码，来自于opencore-Universal Asynchronous FIFO Verilog design code, from opencore
code
- Simulation and Synthesis Techniques for synchronous FIFO Design
leap-year
- 一个FIFO设计的例子，例子简单，但很经典。 是学好数字设计的好开端。-A FIFO design examples, example of simple, but very classic. Learn digital design is a good start.
asyn_fifo
- verilog编写的异步fifo源代码，asyn_fifo.v为顶层，调用其他四个文件-asynchronous fifo prepared Verilog source code, asyn_fifo.v for top-level, call the other four documents
fifo
- 实现fifo的基本功能。使用Verilog能够实现的同步数据先入先出功能，简单易懂，并带有相应的测试文件-Fifo realize the basic functions. Be able to use the Verilog implementation of the synchronous data FIFO functions, easy to understand, with the corresponding test file
asynFifo
- 异步fifo在IC设计中，非常重要；是异步时钟域同步方法-Asynchronous fifo in IC design, is very important are asynchronous clock domain synchronization
myfifo_bb
- fifo(1-6:1):using ip-code and rd wd interface-fifo:using ip-code and rd wd interface
DIGITALLOCK
- Verilog code for Digital lock
fifodd
- 一个深度为32，字长为8_bit FIFO（先进先出）寄存器，有寄存器空、寄存器满和寄存器溢出信号。-A depth of 32, word length for 8_bit FIFO (FIFO) register, a register space, register and register full signal overflow.
90ca241e-4f51-4333-9868-0d7aceddcb39
- lcd驱动程序的verilog代码，最基础的功能实现，rt1602-lcd
FIFO_IN_VERILOG
- 基于Verilog的fifo的实现源码和测试文件-Fifo-based realization of the Verilog source code and test file
FIFO
- FIFO以及跨时钟域的同步问题。 FIFO有分离的地址总线和用以读写数据的数据通道，以及指示堆栈状态（满、将满等）的状态线。-FIFO as well as cross-clock domain synchronization. FIFO have separate address bus and read and write data to the data channel, as well as the instructions state stack (full, will be fu
FIFO
- 利用Verilog实现了一个FIFO，包含几个模块文件，适合初学Verilog的朋友，含测试代码。-Verilog achieved using a FIFO, a document contains several modules, suitable for novice Verilog friends, including test code.
RT_8051_memory
- 8051 RT Memory Verilog-8051 Memory