4×4键盘扫描的verilog 代码,在CPLD板上实现

东南大学Verilog讲义 Verilog 语言作为CPLD和FPGA开发语言,比VHDL相比有更多的优势.-Southeast University Verilog notes Verilog language as CPLD and FPGA development language than VHDL have more advantages in comparison.

An overview of Finite State Machines. FSMs are an important aspect of FPGA and CPLD desig using VHDL and Verilog-An overview of Finite State Machines. FSMs are an important aspect of FPGA and CPLD desig using VHDL and Verilog

温度传感器采集数据给cpld，然后由串口上传到上位机；编程语言是verilog；-Temperature sensor collected data to the the cpld, then uploaded to the host computer by serial programming language verilog