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jiaotongxinhaodengkongzhiqidesheji
- 本论文主要介绍了红、绿、黄三色交通信号灯较简单的数字逻辑控制电路设计及其原理。本设计方案由定时器、分频器、扭环形计数器、十进制减法器及七段显示译码器实现交通灯红、黄、绿三色的自动切换，在切换灯光颜色的同时进行时间定时状态的切换，使整个交通灯系统得以按照事先设定的定时时间顺利运转。-This paper focuses on the red, green, yellow three-color traffic signal control of the relatively simple digi
si4133-datasheet
- 该Si4133是一个单片集成电路，既执行IF和双频 RF合成为无线通信应用。在Si4133 包括三个和VCO，环路滤波器，参考和VCO分频器，相位 探测器。除法和可编程掉电设置与threewire 串行接口。-The Si4133 is a monolithic integrated circuit, both the implementation of the IF and dual-band RF synthesis for wireless comm
frequencydivider
- 计数器和分频器的PDF资料，供大家参考哈。希望对大家有用-Counter and frequency divider of the PDF information for your reference ha. Want to be useful to everyone
divider
- function [a_width-1 : 0] DWF_div_uns // Function to compute the unsigned quotient // synopsys map_to_operator DIV_UNS_OP // synopsys return_port_name QUOTIENT input [a_width-1 : 0] A input [b_width-1 : 0] B reg [a_width
RTC
- RTC 实时时钟，主要用于实现长时间计时。模块包括可选8：1 分频器，一个定时器T14，及一个32 位RTC 计数器。本例程介绍RTC的DAVE配置以及KEIL的编程指导-RTC Real Time Clock, mainly used to achieve a long time. Module includes an optional 8:1 divider, a timer T14, and a 32-bit RTC counter. The routine introduction of
digitalfreq
- 由于本人没有多少很好的源码，所以只能上传目前所做项目的相关参考文献资料。资料一的内容是数字分频器的参考文献，在fpga中数字分频器用的很多，文献对于设计小数分频器有一定的参考价值。-I am not much good as the source, we can only upload now doing projects related reference materials. Information content of a digital divider references in the
Combinational_Divider_in_FPGA
- Three VHDL codes for combinational divider with implementation results for Xilinx Spartan FPGAs-Three VHDL codes for combinational divider with implementation results for Xilinx Spartan FPGAs
DividerInt
- VHDL source code for combinational divider with integer types
DividerSLV
- VHDL source code for combinational divider with standard_logic_vector types
DividerSLVcompact
- VHDL source code for combinational divider with standard_logic_vector types, more compact version with lower resources requirement
power_divider_based_ADS_simulation
- 这是一个基于ADS的功分器制作的PPT，从理论到实践仿真，比较全面，以供参考。-power divider based ADS simulation.
DPLL
- 数字锁相环频率合成器的设计,鉴相器、环路滤波器、数控振荡器、反馈分频器-Digital PLL frequency synthesizer, phase detector, loop filter, NCO, feedback divider
lem
- 用分压器测量30～300Hz交流电压时的问题Measured with a voltage divider 30 ~ 300Hz AC voltage problem-Measured with a voltage divider 30 ~ 300Hz AC voltage problem
134946
- The CS5460A is a highly integrated power measurement solution which combines two Analog-to-digital Converters (ADCs), high-speed power calculation functions, and a serial interface on a single chip. It is designed to accurate
23824648pinlvji
- 1. 测量信号:方波 ； 2. 测量频率范围: 1Hz~9999Hz 3. 显示方式: 4位十进制数显示 4. 时基电路由 555 定时器及分频器组成, 555 振荡器产生脉冲信号,经分频器分频产生的时基信号,其脉冲宽度分别为: 1s, 0.1s 5. 当被测信号的频率超出测量范围时,报警. -Measuring signal: square wave measurement frequency range: 1Hz ~ 9999Hz display: four d
Tx
- 主要是8201对音频的一些处理，包括分频和传送-8201 pairs of audio processing, including divider and transmission
fenpinqisheji
- 实现分频功能，用VHDL语言实现，也可适当改变参数，实现任意分频-Implementation divider using VHDL, it may be appropriate to change the parameters to achieve any divide
verilog_example
- verilog实例，多路器，除法器，数字跑表的多种实现方法-verilog example, the multiplexer, a divider, a digital stopwatch many implementations
VHDL-divider
- 8位数除法器，用的软件是quartus，被除数是8位的，除数4位-8-digit division, software quartus dividend is 8, the divisor 4
COP2000-experimental-instrument
- 计算机组成原理 利用COP2000实验仪自行设计指令系统实现乘法器和除法器实验指导-Principles of Computer Organization the use of COP2000 experimental instrument design their own instruction set multiplier and divider experimental guidance