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tetris
- 俄罗斯方块游戏。可改变游戏速度，实现了最简单的功能，包含分频、按键防抖，可在8*8点阵上显示。-Tetris game. You can change the speed of the game, the most simple functions contains divider button image stabilization, 8* 8 dot matrix display.
CPLD
- 基于lattice的CPLD时钟除频的编程与设计。-Lattice-based CPLD clock divider programming and design。
2
- 关于FPGA的分频代码,是vhdl语言编写的，可能比较简单，但比较实用。-Divider code on the FPGA
EDA
- 基于 CPLD/FPGA用原理图和VHDL语言混合设计实现了一多功能通用分频器。-CPLD/FPGA-based mixed schematic and VHDL language design and implementation of a multi-function universal divider.
Clk_Divider
- System Verilog Clock Divider module done with impementation, contains the implementes modules inside too.
seq_div
- 除法器设计 样例程序-Divider design sample program
Masseffect-3---Jane-Shepard
- 超級好用 25M~100HZ的除頻器 寫了好久 超級實用 歡迎下載-Super easy to 25M ~ 100HZ of divider wrote a long time super practical welcome to download
Dll-Files
- clock divider code for vhdl
wang
- vhdl语言的四位二进制除法器，带有详细的流程图及计算原理-vhdl language of four binary divider, with a detailed flow chart and calculation principles
div_clk17
- 手写时中分频，17分频，用状态机写成，之欧诺个两个过程语句简单明了易懂-Handwritten carve frequency divider 17, the state machine languages, the two processes Uno a statement, jianji8e clear and understandable
001
- 分频器的四连体数码管显示源代码以及对其分析-The four-piece divider digital display source code and its analysis
fp
- 实现60MHZ到40KHZ的分频，分频后壳实现外部晶振和内部晶振的时钟统一。-60MHZ to achieve 40KHZ divide the shell to achieve external crystal oscillator and internal clock divider after unification.
zhen1
- 本文设计的数字分接器是由帧同步提取模块、位同步提取模块、帧同步移位和时序信号恢复模块、分路器模块、串/并转换电路模块五部分组成-Digital tapping machine is designed in this paper by the frame synchronization extraction module, a synchronous extraction module, the displacement of frame synchronization and timing si
Microsoft-Word--(11)
- 分频器程序，可以实现分频器的功能，很方便的使用可以实现分频器-Divider program, you can achieve divider function, it is convenient to use the divider can be achieved
cpld
- CPLD与电子CAD报告 VHDL中的并行语句、进程 信号、变量、顺序语句 分频器、计数器、译码器、状态机 数字钟综合设计-CPLD and VHDL electronic CAD report in parallel statement, the process signals, variables, sequential statements divider, counter, decoder, an integrated digital clock state machine des
fec_code
- The Slow Peripherals Clock Group includes the McBSPs, I2C, and the UART. The input clock to this clock group is taken the output of divider 2 (D2). by default, the divider is set to divide its input clock by four, but the divide value can be chan
egprog
- EG8010 is a digital pure sine wave inverter ASIC (Application Specific Integrated Circuit) with complete function of built-in dead time control. It applies to DC-DC-AC two stage power converter system or DC-AC single stage low power frequency tra
clk_divR
- frequency divider into reglable frequence
7771_reg-voltage_ApplicationNote
- There are variety ways of building 3.3V power supply, such as using voltage divider, voltage regulator and DC-DC converter.
AC220V-DC4.2V
- 本设计设计手机充电器系统，实现由交流220V电能到直流4.2V电能的转换，进而为手机等设备充电。在系统控制中采用了变压、整流、滤波、稳压、分压、电压检测等电路，并且具有一定的充电提示和充满电自动断电的功能。 本设计采用Proteus（V7.1）软件仿真进行演示。-Based on Proteus simulation design phone charger system, implemented by 220V AC power to DC 4.2V power conversion. I