SPI的Verilog实现(非常的全面和详细，还带有SPI算法的注解).-SPI in Verilog implementation (a very full and detailed, but also with the SPI algorithm annotation).

a UART model with FIFO buffer, design with verilog

The use of hardware descr iption languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level descr iption not only increases design productivity, but also provides unique advantages for design verif

基于ISE 用verilog编写的uart串口通信源码-Based on the ISE written in verilog uart serial communication source code