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VLSI_Architectures_for_ECC
- This thesis devoted to several efficient VLSI architecture design issues in errorcorrecting coding, including finite field arithmetic, (Generalized) Low-Density Parity- Check (LDPC) codes, and Reed-Solomon codes.-This thesis is devoted to sever
labQ2
- Source codes for verilog fifo for spartan 3
BCH
- 有效的并行编码器对于长BCH编码的 大家放心 真的号死后和很好评的-Area efficient parallel decoder architecture for long BCH codes
RS_decode
- RS编译码算法的实现 RS 码以其强大的纠突发错能力, 被广泛应用于各种差错控制场合。本文讨论了RS 码的编码和译码算 法及其软件实现。-Implementation of RS encoding and decoding algorithm for RS codes with its powerful burst error correcting capabilities, error control is widely used in various occasions. This
codes
- verilog code for traffic light controller and test bench for verification purpose
codes
- some basic codes in verilod and thier test benches for understanding the basic verilog codes
ModelSim_SE_Plus_v5.7F_Real_Working
- model sim simulator of vhdl and verilog codes
source
- Codes for FFT using Verilog language
ldpc
- 移动通信技术中信道编码的LDPC码的Verilog hdl 实现-Verilog hdl channel coding of mobile communication technology to achieve LDPC codes
MS_LDPC
- 移动通信技术中信道编码的LDPC码的译码Verilog hdl 实现-Decoding Verilog hdl channel coding of mobile communication technology to achieve LDPC codes
convolution
- convolution codes using verilog language for FPGA