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pld MegaWizard Plug-In Manager
- 利用QuartusII的"MegaWizard Plug-In Manager", 设计输入数据宽度是4bit的ADD、SUB、MULT、DIVIDE、COMPARE 把它们作为一个project,DEVICE选用EPF10K70RC240-4，对它们进行 时序仿真，将仿真波形（输入输出选用group）在一页纸上打印出来。 2.利用QuartusII的"MegaWizard Plug-In Manager"中的LPM_
jc2_ver
- Johnson counter with verilog
bai4
- a 16 bits counter using verilog
a_time_counter_using_verilog
- a time counter using verilog
a_bcd_counter_using_verilog
- 3 bits bcd counter using verilog
Counter_AD
- Parametrized System Verilog code for a Counter with an increade, decrease switch (AD)
count_1000
- 适用于verilog hdl初学者——0-999加法计数器，内带vwf波形仿真-Suitable for beginners 0-999 adding counter verilog hdl, which with vwf waveform simulation
counter
- 利用verilog编写的分频计数器，包括0.01s,1ms，1s三个计数器，可适用于ise14.7开发环境-Use verilog to write a crossover counter, including 0.01s, 1ms, 1s three counters, applicable to ise14.7 development environment
trtgh4P944
- 8位十进制计数器,采用Verilog语言编写，成功与大家分享一下-8-bit decimal counter, use Verilog language, to share with you about my success
counter
- 用verilog实现基于FPGA的计数器功能实现-Realization of counter function based on FPGA with Verilog