ROM using file.suite in design a simple CPU

基于FPGA控制的ASIC CPU系统设计，全是用VERILOG代码编写，可以做加减乘除运算 -FPGA-based control ASIC CPU system design, all made with VERILOG code writing, arithmetic operations can be done

CPU设计与实践实验报告 70多页，详细说明各模块工作原理-cpu design report

简易处理器要求，应用QUARTUS软件和模块化、层次化的设计方法进行设计， 对各模块进行必要的仿真验证。-Simple processor requirements, the application of QUARTUS software and modular, hierarchical design method for design, Simulation and verification are carried out for each module.