搜索资源列表
CPLD任意分频输出 VHDL
- CPLD任意分频输出 VHDL,调试通过
任意分频代码(VHDL)
- 任意分频代码(VHDL)
any_div_freq
- 可以对输入时钟任意分频(整数或小数),带Quartus II 完整项目文件.-Can be arbitrary points on the input clock frequency (integer or decimal), with complete Quartus II project document.
divider
- 该模块为分频器，将1KHZ的时钟频率分频成每分钟一次的时钟频率 事实上，该源码可以实现任意整数的分频，主要让N的值设置好相应的数字-The module for the divider, the clock frequency 1KHz frequency per minute into the first clock frequency In fact, the source can be any integer frequency, mainly to allow the value o
clock_divider
- 任意小数分频器产生原理，及详细说明文档，任意数分频(包括奇偶数和小数)的设计方法(含VHDL例子)-Generate arbitrary decimal divider principle, and detailed descr iption of the document, arbitrary number of sub-frequency (including the odd-even numbers and decimals) design methods (including VHDL
fq_div
- 一种实现任意整数分频的ＶＨＤＬ源代码，已经经过调试-Achieve an arbitrary integer divider of the VHDL source code, has been testing
integerdivider
- 一个任意整数分频程序,采用VHDL语言编写，编译通过-An arbitrary integer frequency procedure for the VHDL language, the compiler through
fdiv
- 基于Quartus II的数控分频器的项目设计，实现对时钟信号的任意进制分频，包含了项目文件和VHDL源代码-NC-based prescaler Quartus II project design, implementation of the clock signal of arbitrary frequency band, including the project files and VHDL source code
ghzfchsa
- 数控分频器，可实现50m以内任意整数分频-NC divider can be realized within 50m of arbitrary integer frequency
VHDL
- 用VHDL写的代码，实现任意整数分频，自己只要修改分频参数即可。希望对大家有用-Written in VHDL code used to achieve arbitrary integer frequency, their frequency as long as the modified parameter. We hope to be useful
bxfsq
- 用VHDL代码实现的0-40000任意分频,具体分频数可以自己参考进行修改.并用matlab写好各种波形图的MIF文件,然后实现FPGA的一个多功能波形生成器! (平时的课程设计)-Achieved using VHDL code 0-40000 arbitrary frequency, the specific sub-frequency reference can be modified. Matlab written by a variety of waveforms of MIF fil
ryfp
- 任意分频,可以自动生成Hdl代码，图形界面操作简单，功能独特-Arbitrary frequency can be automatically generated Hdl code, graphical interface is simple, unique features
int_div
- 基于fpga的任意频率的可计数分频器（奇偶数皆可）-frequency divide
div
- verilog任意分频电路实现，仿真效果非常好-div dclk
fenpinVHD
- 任意分频的VHDL 任意分频的VHDL-Any sub-band frequency VHDL any sub-sub-frequency VHDL arbitrary VHDL
DDS-FENPIN
- DDS实现任意小数分频,2.4.6，8和小数分频-DDS to achieve any fractional frequency 2.4.6,8 and fractional-N
clk_div_n
- 时钟任意分频模块，输入为主时钟和分频数，输出为主时钟/分频数。-Clock divider
N_Separate-frequency-device
- 可以输入0到2的5次方的任意分频的分频器-Separate frequency device
random frenquency division
- verilog任意分频代码，作为新思路参考(veriliog code used as reference to new idea)
fenpin51
- 任意整数分频器，输出方波可调占空比（已仿真下板子验证）第一个系数为分频系数，第二个为高电平所占整个方波的比例(Arbitrary integer frequency divider, output square wave adjustable duty cycle (has been simulated under board verification), the first factor for the frequency division coefficient, the second fo