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rs-codec-8-4
- encode.v The encoder syndrome.v Syndrome generator in decoder berlekamp.v Berlekamp algorithm in decoder chien-search.v Chien search and Forney algorithm in decoder decode.v The top module of the decoder inverse.v Computes multiplic
key_prog
- 简单易懂的4*4键盘扫描及显示程序。对编写其他形式的键盘扫描程序有一定的指导意义.-easy-to-read 4 * 4 keyboard and display program. To the preparation of other forms of keyboard scan procedures are certain guiding significance.
cupdesign
- 初学cup设计的极佳资料，详细介绍了cup设计的各个流程及各组件的设计-novice cup of excellent design, detail design of the cup and the various components of the process design
alu_32_bit
- verilog 32-bit ALU-verilog 32-bit ALU
pwm_VerilogHDLV1.1
- 本软件在CPLD上实现数字PWM控制，用Verilog HDL语言编写，在MAX ＰＬＵＳ ＩＩ调试成功，可用-the software on the CPLD digital PWM control, using Verilog HDL language, MAX PLUS II in debugging success can be
SPI_verilogHDL
- 本原码是基于Verilog HDL语言编写的，实现了SPI接口设计，可以应用于FPGA,实现SPI协议的接口设计.在MAXII编译成功,用Modelsim SE 6仿真成功.-primitive code is based on Verilog HDL language, and achieving the SPI interface design, FPGA can be used to achieve agreement SPI interface design. MAXII success
pwm_higt
- modelsim设计的可调占空比的方波程式-modelsim designed adjustable duty cycle of the square wave program
8051-core
- 8051单片机是一种应用最广泛的单片机.它的内核设计非常精简,这是用Verilog硬件描述语言写的8051单片机内核-8051 is a most widely used SCM. Its kernel design has been streamlined, This is used Verilog hardware descr iption language to write the 8051 microcontroller core
LED_driver_IP_for_SOPC_BUILDER
- 一个数码管的驱动IP for SOPC BUILDER. 是学习SOPC的一个参考范例.-one of the driving digital IP for SOPC BUILDER. Learning is a Senate SOPC Examples examination.
26_1000
- 若干VHDL语言的源代码，我觉得应该用用仅供参考-several VHDL source code, I think that should be used for reference purposes only
CpldandEepromI2c
- verilog 编写的I2c协议程序，用于cpld读写EEPROM-verilog I2c agreement prepared by the procedures for cpld writable EEPROM
div5
- 简单的VERILOG五分频电路描述，可综合。已经过检验-simple verilog 0.2-frequency circuit descr iption can be integrated. Have been tested
TLC5510APhase
- 运用TLC5510A高速(20M),扫描出波形,测量相位差,两个TLC5510A测两个波形. -TLC5510A use of high-speed (20M), scanning waveform, phase difference measurement, Measuring 2 2 TLC5510A waveform.
rtl_DRAM
- 本程式為使用Verilog語言寫控制DRAM的控制模塊, 可以簡易的控制DRAM IC, 本程式已經過系統驗證.-program for the use of the Verilog language to write the control of DRAM control module, be easy to control DRAM IC, the program has been systematically verified.
Seg7
- FPGA Seg7七段顯示器模組副程式 Veliog -paragraph 107 Display module subroutines Veliog
usb_phy
- umti协议中的usb1.1的verilog原文件，可公实现usb2.0做参考-umti the agreement usb1.1 verilog the original documents, the public can refer to achieve usb2.0
usb1_funct
- usb1.1的verilog源代码。以及其测试仿真文件，现在很难找其测试文件既testbench-usb1.1 verilog the source code. Simulation and test document, and now it is very difficult to find the paper test testbench
ver6.0
- windowsxp/2000下驱动程序开发软件winddriver6.0-windowsxp/2000 under driver development software winddriver6.0
16bit_booth_multiplier_STG
- verilog程序，实现两个16bit数乘法，采用booth算法，基于状态机实现，分层次为datapath和controller两个子模块，testBench测试通过-verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for datapath controller and two sub-mo
dirital_clock_7
- verilog实现电子时钟模块，输入60Hz时钟信号和复位，输出时分秒，共6位，每位7段输出用于驱动-verilog electronic clock module, 60Hz input clock signal and reset, Minutes exportation, a total of six, each of the seven drivers for output