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final_code
- mining source code written in Verilog
mt48lc2m32b2
- SDRAM控制核，已经经过测试，完全可以稍加修改后应用-SDRAM control nuclear, has been tested, we can use a slightly modified
SDRAM_C
- SDRAM控制核，已经经过测试，完全可以稍加修改后应用-SDRAM control nuclear, has been tested, we can use a slightly modified
time_clock
- 实用闹钟的verilog代码。不是vhdl的！经过ldv验证-practical alarm the Verilog code. VHDL is not! After certification ldv
cal_verilog
- 计算器芯片的verilog实现代码！ 时序仿真成功-calculator chips to achieve the Verilog code! Timing simulation success
SVDrink
- Systemverilog 编写的贩卖机代码-Systemverilog preparation for the sale code
Lab_ISE_Led
- vhdl实例教程，其中的例子适合新手演示使用，肯定会有帮助的。-VHDL example tutorial, an example of the use for novice demo, it will certainly help.
cpldtraffic
- 交通灯信号的ｆｐｇａ实现。通过ｖｅｒｉｌｏｇ语言编程，在ｆｐｇａ上调试通过。-traffic signal lights they simply achieve. Through the Verilog language programming, they simply passed on debugging.
fpgasong
- 以verilog HDL 语言编写的一首歌曲，可供初学者借鉴-to Verilog HDL language of a song, draw for beginners
calendar_clock
- 用verlog HDL写的电子日历,可以显示年,月,日和时间,具有闹铃的功能-using HDL to write electronic calendar, it shows the year, month, day and time, with alarm function
cardPhone
- 卡式计费电话电路,用verilogHDL编写,主要完成模拟真实电话的功能-card billing telephone circuits, verilogHDL prepared with the major simulate the real phone function
key_scan1
- 用verilog实现的四乘四键盘程序,在Quartus II上编译通过并成功-achieved using Verilog 4 x 4 keyboard procedures, the Quartus II compiler on the adoption and successful
generic_fifos
- 用HDL语言编写的通用fifo源码，通过对fifo的宽度和深度进行配置，可以产生我们所需要的fifo，还包括fifo的测试程序和仿真Makefile脚本-with HDL prepared by the General fifo source, fifo of the breadth and depth configuration, can produce what we need fifo. also included fifo testing procedures and simulatio
USB2.0_rtl_ipcore_verilog
- 经过门级网单验证的USB2.0 IP核 RTL代码-net after gate-level verification of USB IP Core RTL code
adder16bit
- 16位高速加法器，采用verilog语言编写，已经成功仿真，能够运行
statemachine_mult
- veilog实现的状态机乘法器.可以参考-veilog achieve the state machine multiplier. Can reference
VSR4_3
- 甚短距离互联（Veryshort reach VSR）协议编成实现-very short distance from the Internet (Veryshort reach VSR) composition to achieve agreement
asi
- 在公司做的一个用FPGA实现的数字电视系统中 ASI转TS流的程序-done in the company of an FPGA using the digital television system to ASI TS flow procedures
counter_7seg
- 带分频器的bcd计数电路设计，verilog源码-dividers with the bcd count circuit design, Verilog source
Arbiter
- Arbiter.v verilog实现 三路请求，使用循环策略的仲裁器 含有看门狗电路-Arbiter.v Verilog achieve three road request, the use of recycled strategy for containing the arbitration watchdog circuit