搜索资源列表
syn_fifo
- 基于systemverilog的异步fifo-fifo of design ，system verilog
Final_Phase
- Frequency Counter of Signal Generator
8051_FTEST_K4X4(NO.1)
- 8051_FTEST_K4X4 带按键的4x4的 等精度频率计！-8051_FTEST_K4X4 with key 4x4 and other precision frequency counter!
verilog
- 这是一款学习板的基础实验代码，对于FPGA学习有很好的指导作用。-This is a learning board is based on experimental code, good for the FPGA learning guide。
78279164c15_add
- 非常有用的资料 中国传媒大学上课所用资料-this is a very useful way to study digital signal process
viterbi_decoder_programs
- viterbi decoder programs
quartus_tutorial
- This an adder-subtractor, with two inputs: one to add another two inputs, and the other to subtract it-This is an adder-subtractor, with two inputs: one to add another two inputs, and the other to subtract it
dct_verilog
- Implementation of one dimensional Discrete cosine transform using verilog for FPGA implementation
digital-paobiao
- 是在50M CLK 下实现的，通过在数码管上实现进位显示-Digital PaoBiao，which works in the 50 M CLK is under implementation, through pipes in the digital realization that carry
mux_case
- 用case 语句描述的4 选1 MUX源代码程序实现-case4（1） ，VHDL&verilog
block2
- 阻塞赋值方式，描述的移位寄存器2verilogHDL源代码实现-Block verilogHDL
account
- 电话计费器程序的VerilogHDL源代码实现-cellphone account ，verilogHDL
traffic
- 绿灯、黄灯和红灯交通指示灯的verilog HDL程序源代码-traffic lamp ，red,yellow,green,verilog HDL
clock
- 多功能数字钟的Verilog ＨＤＬ源代码程序的实现-ｍｕｔｉｌ－ｆｕｎｃｔｉｏｎ ｄｉｇｉｔａｌ ｃｌｏｃｋ Verilog ＨＤＬ
mux
- Mux design in Verilog
examples
- 改程序的功能是可以产生三角波方波，并且用两个计数器完成计数-Change program can generate the triangular wave square wave, and two counters count
lcd
- lcd program in verilog designing
chapter9
- 一个别人写的ＵＡＲＴ ｖｅｒｉｌｏｇ程序，希望对大家有帮助-A UART verilog program written by someone else, we want to help
ad
- 程序是本人亲测，可实现fpga对ads804的高速数据采集，和输出。利用了fpga的fifo和ad芯片每六个时钟数据更新一次的原理-The program I pro-test, the FPGA the ads804 high-speed data acquisition and output. The principle of use fpga fifo and ad-chip is updated once every six clock data
vgav2
- This verilog vga test circuit