搜索资源列表
CIC滤波器matlab代码
- CIC滤波器matlab代码 D=5; r=D; fs=1e5; S3_cic=conv(conv(ones(1,D),ones(1,D)),ones(1,D)); %三个单级卷积 [h3,f3]=freqz(S3_cic,1,1000,fs); plot(f3/(fs/2),20*log10(abs(h3))-max(20*log10(abs(h3))),'r','LineWidth',1.4) ylabel('\fontsize{12}\bf幅度响应（dB）') xlabel('\fonts
cic512.rar
- 5阶cic滤波器，抽取12倍，的verilog程序，已经通过仿真验证，一、具有很高的速率,5-order CIC filter, collected 12 times the Verilog procedures are by simulation, one with a very high rate
cic5
- matlab CIC滤波器程序,5级CIC滤波器的设计,采用优化结构，采样速率在积分器后降低；-matlab CIC program,five taps design.
CIC_DEC
- CIC抽取滤波器设计，CIC滤波器采用5阶8倍抽取。-CIC decimation filter design, CIC filter order of 8 times 5 samples.
123
- matlab实现的多相滤波器，cic抽取D=5时例子，及级联型的cic的程序。-matlab implementation of the polyphase filter, cic examples taken D = 5 时, and the cascade of cic procedures.
c19_CICfilter
- 精通verilog HDL语言编程源码之5--CIC积分梳状滤波器设计-Proficient in verilog HDL source language programming of 5- CIC Integrator Comb Filter Design
xugc
- cic512 5阶cic滤波器，抽取12倍，的verilog程序，已经通过仿真验证 -5CIC
CIC6_fir_comp_mlab
- CIC补偿滤波器设计，CIC滤波器采用5阶6倍抽取设计。-CIC compensation filter design, CIC filter 5 samples 6 times the design stage.
CIC8_fir_comp_mlab
- CIC抽取补偿滤波器设计，CIC滤波器采用5阶8倍抽取。-CIC compensation filter design samples, CIC filter order of 8 times 5 samples.
CIC4_fir_comp_mlab
- CIC抽取补偿滤波器设计，CIC滤波器采用5阶4倍抽取。-CIC compensation filter design samples, CIC filter order 4 times using 5 samples.
CIC_DEC_3
- CIC抽取滤波器设计，CIC滤波器采用5阶3倍抽取。-CIC decimation filter design, CIC filter order 3 times 5 samples.
CIC_DEC_4
- CIC抽取滤波器设计，CIC滤波器采用5阶4倍抽取。-CIC decimation filter design, CIC filter order 4 times using 5 samples.
CIC_DEC_6
- CIC抽取滤波器设计，CIC滤波器采用5阶6倍抽取。-CIC decimation filter design, CIC filter stage 6 times 5 samples.
cic
- 在MATLAB2007A/SIMULINK环境下用DSP BUILDER8.0实现了五级CIC，解决了溢出问题。生成了可用的VHDL文件。- DSP BUILDER8.0 A 5 stages CIC filer is realized in MATLAB2007A/SIMULINK by using DSP Builder 8.0.The overflow problem is resulved.Useful VHDL files are generated at last.
cic5
- 5级级联CIC滤波器的VHDL程序。CIC是最简单最易实现的低通滤波器，通常CIC滤波器如果采用单级，带外衰减不够，因此需要级联使用，5级级联的CIC带外衰减能够满足大多数的设计要求。而带内的衰减可以采用补偿滤波器抵消掉绝大部分。-the code of 5-CIC
cic_filter
- 5阶cic滤波器 使用vdhl编写 下载后将tb代码烤出 新建，然后综合仿真！-5 cic filter using vdhl written order to download the code will tb baked New, and then integrated simulation!
FPGA_CIC
- 用Count计数法实现5级CIC滤波器，能够提前或者延迟一个周期采样。能综合-Implementation level 5 CIC filter with Count counting method, one can advance or delay the sampling period.
CIC_desgin
- 1）设计不同长度的单级CIC滤波器，并plot出阶数为2、5、7、8的CIC滤波器幅频特性 2）设计出5级CIC滤波器(1) design a single level CIC filter with different lengths, and the amplitude frequency characteristics of the plot order of 2, 5, 7, 8 of the CIC filter 2) a 5 level CIC filter is designe