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C51-counter.rar
- 用C51座位CPU的计算器，具备8位数加减乘除功能。P0作为数码管的段控制，P2作为数码管位显示控制，P3控制4x4键盘阵列。,C51 as the CPU, the counter can process 8 bit numbers "+,-,*,/". P0 contro the LED and P2 for which bit,P3 oprate the keyborad
Counter
- 描述的是一个含计数使能异步复位和计数值并行预置功能8 位的加法-With descr iption of a count enable asynchronous reset and preset features of numerical parallel 8-bit adder
cnt8bc
- 8位加减带异步复位计数器，使用双向输入管脚- Design an 8-bit up and down synchronous counter in VHDL with the following features: The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered. The counter is with an asynch
11
- cnt6.bdf 六进制约翰逊计数器 counters.vhd 不同功能的简单计数器 count60.vhd 60进制计数器 count60.bdf 60进制计数器 counter_1024.vhd 8位二进制计数器 counter_1m.vhd 16位二进制计数器 counter.vhd N进制计数器-M Johnson cnt6.bdf six different functions counters.vhd counter simple counter count
shiyan6
- 一个8位的十进制频率计数器,功能经过测试.-An 8-bit decimal frequency counter, function tested.
shifter
- 完成一个加速器设计，全加器，具 8位计数器-Complete a accelerator design, full adder, an 8-bit counter
DVF
- 数控分频器的设计数控分频器 端口定义： CLK：时钟输入 D[7..0]：预置数据 Fout：分频输出 说明： D[7..0]作为8位加1计数器的初值，初值越大，分频输出频率越高，反之越低， -NC NC divider divider port the definition of design: CLK: Clock input D [7 .. 0]: preset data Fout: frequency output that: D [7 .. 0] as
UpDownCounter
- 8-Bit Up Down Counter Verilog Code
8-bitcountercanbepresetthereproteussimulationsourc
- 可预置的8位计数器源程序还有proteus仿真-8-bit counter can be preset there proteus simulation source code
Chapter11-13
- 第十一章到第十三章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个
counter
- 8 bit counter-8 bit counter!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
HW3
- Write VHDL codes to model an 8-bit counter that counts every second. It counts from your last two digits of your student ID to your next two digits of your student ID. If the last two digits are greater than the next two digits, the counters counts d
8-Bit-Up-Counter-With-Load
- 8位计数器与负荷 -----------------------8位计数器与负荷 -8-Bit Up Counter With Load 1------------------------------------------------------- 2-- Design Name : up_counter_load 3-- File Name : up_counter_load.vhd 4-- Function : Up counter
8-jinzhi-counter
- 8进制计数器 每计数八次进一次位，vhdl语言的基础程序，对初学者很有帮助-8 binary counter into a bit of each of eight counts, vhdl language based program, very helpful for beginners
8-bit-decimal-frequency-meter
- 利用FPGA，实现8位十进制频率计功能。高效，实用。-Using FPGA, to achieve 8-bit decimal frequency counter function. Efficient and practical.
The-8-down-counter-design
- 带异步复位和计数使能控制的8位二进制减法计数器设计-With asynchronous reset and the count enable control 8 bit binary subtraction counter design
8-Bit-Up-Counter-With-Load
- 8位计数器，能实现加减计数，经过ise 测试仿真了。符合逻辑-8-bit counter, plus or minus count after ise test simulation. Logical
PLC-8-bit-counter-proteus
- PLC 8位计数抢答器的程序已及仿真程序图-PLC 8-bit counter Responder program has been and simulation program in Figure
verilog-8-bit-Gray-Counter
- Verilog 8 bit Gray Counter
Count8
- vhdl code for eight bit counter