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alu_inverter
- 4bit ALU 利用vhdl语言编写的4位ALU 开发环境是在windows下-Band ALU using VHDL language prepared by the four ALU is a development environment under Windows
PIPE_LINING_CPU_TEAM_24
- 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。 能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,
16bitalu
- 16 bit alu using the vhdl it has 16 function perform by control unit with 4 control signal
SYNTHPIC.ZIP
- The Synthetic PIC Verion 1.1 This a VHDL synthesizable model of a simple PIC 16C5x microcontroller. It is not, and is not intended as, a high fidelity circuit simulation. This package includes the following files. Note that the licen
alu_code_asif
- vhdl code for ALU.i think by reading his code..it will be very easy for you to design an Alu.
alu_struct
- ALU written in VHDL, tested in FPGA advantage, there will be no support on this code. All right reserved by developer.
ALU_VHDL_code
- ALU逻辑运算单元计算器的VHDL源代码，已通过FGPA验证，绝对正确。-ALU ALU calculator VHDL source code has been verified by FGPA absolutely correct.
project
- 利用VHDL实现三个简单的程序：BCD加法器；ALU算术逻辑单元；简单密码锁设计，具有输入密码和数据比较两种功能，由M决定是写入还是开锁。而数据写入是采用列地址与输入数相结合的的方法，存入初始密码；开锁时，密码以输入，再输入的数据逐个与输入的一组数据比较，完全吻合则开锁。-The use of VHDL to accomplish three simple procedures: BCD adder ALU arithmetic logic unit simple lock design,
ALU_mo
- ALU architecture for a microcontroller by using VHDL synthesis
alu071221136
- 利用VHDL书写的一个简单的算术逻辑部件ALU，在QuartusII下编译通过-Use VHDL to write a simple arithmetic logic unit ALU, compiled by the QuartusII
VHDLcodes
- Behavioral descr iption of ALU, RAM MODULE, ROM MODULE, DIVIDE BY N COUNTER, GENERIC DIVIDER 2n+1, GCD CALCULATOR, GCD FSM CODE, JK FLIP FLOP in VHDL . These are fully synthesized codes with optimization.- Behavioral descr iption of ALU, RAM MODULE,
vhdl-pipeline-mips_latest.tar
- pipeline mips in vhdl
alu
- 一个简单的四位alu，用max+plusII运行-a simple 4bit alu by vhdl.You can use max+plusII to text it
SSALU
- VHDL设计8位算术逻辑单元（alu），实现清零、逻辑乘、逻辑加、逻辑异或、算术加、逻辑左移一位、逻辑右移一位等功能-VHDL design eight the arithmetic/logic unit (alu), realize the reset, logic, logic and, by different or, arithmetic and logic, logical moves left a, logic move to the right a etc.
ALU
- 用VHDL编的简易的alu运算器，可完成加减乘法等功能-VHDL code with the simple alu computing device, to be completed by addition and subtraction multiplication etc.
new_yasodai_code
- ile Format: PDF/Adobe Acrobat - Quick View by SS Basha - 1963 - Related articles HIGH SPEED MULTIPLIER FOR ALU S USING MINIMAL ... VHDL codes for 8x8-bit signed numbers and successfully simulated and .... a partial product is generated from the m
Jammuna_code
- ile Format: PDF/Adobe Acrobat - Quick View by SS Basha - 1963 - Related articles HIGH SPEED MULTIPLIER FOR ALU S USING MINIMAL ... VHDL codes for 8x8-bit signed numbers and successfully simulated and .... a partial product is generated from the m
cpu
- 本代码主要通过VHDL语言描述了一个CPU，包含了MAR,MBR,PC,BR,ALU,ACC等一系列寄存器。-The code is mainly described by VHDL language a CPU contains a series of MAR, MBR, PC, BR, ALU, ACC register.