搜索资源列表
basys_3_sch_public
- basys3详细内部结构布局，各个模块都有。-basys3 detailed internal structure and layout, each module has.
second2
- basys3板子的Verilog环境下的秒表源代码-stopwatch basys3 Environment
Basys3_FPGA
- 介绍xilinx FPGA为核心的basys3板子的用法-Introduction xilinx FPGA as the core of basys 3 board usage
7_VGA
- VGA屏幕上显示出白-红-绿-蓝的彩条信号。基于basys3，软件平台vivado-VGA screen display color signal of white- red green blue. Based on basys3 software platform, vivado
2_digital_clock
- 采用Verilog HDL RTL 描述完成数字钟，基于basys3，软件平台：vivado-Using Verilog HDL RTL to complete the descr iption of digital clock based on basys3 software platform: vivado
5_bluetooth_uart
- 基于FPGA，硬件平台：basys3，软件平台：vivado。描述语言：verilog。封装自己的蓝牙串口IP。蓝牙串口数据传输需要三个模块，分别是波特率生成模块，接收模块和发送模块。-Based on the FPGA hardware platform, software platform: basys3, vivado. Descr iption: verilog. Package your own Bluetooth serial port IP. Bluetooth serial da
6_XADC
- 基于FPGA，硬件平台：basys3，软件平台：vivado。描述语言：verilog。 实现XADC采集双路外部电压输入。-Based on the FPGA hardware platform, software platform: basys3, vivado. Descr iption: verilog. The implementation of XADC acquisition dual external voltage input.
简易数字钟
- 基于basys3的简易数字钟，可用于vivado开发环境入门，功能有计时和显示模块。(Basys3 based simple digital clock, vivado development environment can be used for entry, function, timing and display module.)
CPU
- 基于Basys3的16位CPU设计，含有指令集，可以控制Basys3的LED灯，并且通过板子上的开关，调节流水灯的模式(16 bit CPU design based on Basys3, containing instruction set, can control the Basys3 LED lights, and through the switch on the board, adjust the water lamp mode)
Basys-3-GPIO-2016.4-1
- Test for GPIO for basys3, made by digilent
Basys-3-Keyboard-2016.4-1
- Demo for keyboard, basys3 made by digilent
just_clock
- Just a clock made for basys3 in vivado.
Mux41a
- Basys3 4选一数据选择器代码，初级者学习，在板子上试验过，没问题。(Basys3 4 select a data selector code)
project_PmodMic_PmodAMP2_1
- 用digilent公司的basys3开发板，外接Pmodmic和PmodAMP2模块，实现对声音的采集和复原。程序基于VIVADO 2015.4，附带例化的低通滤波器。实际可用。(Use digisen's basys3 development board, external Pmodmic and PmodAMP2 modules to achieve sound collection and recovery. The program is based on VIVADO 2015.4 wi
project_PmodKYPD
- 用Digilent公司BASYS3开发板和PmodKYPD模块，实现对按键的检测。程序基于VIVADO 2015.4，语言为verilog。(Digilent's BASYS3 development board and PmodKYPD module are used to detect keystrokes. The program is based on VIVADO 2015.4 and the language is verilog.)
FPGA-Projects-master
- FPGA BASYS3 PROJECTS
基于basys3及VGA显示的俄罗斯方块游戏
- 本项目通过FPGA技术实现俄罗斯方块游戏并进行版面及玩法的创新。使用Basys3 FPGA作为主控平台，通过VGA接口显示俄罗斯方块游戏界面，并通过硬件按键模块操作游戏。
USB_Serial1
- 实现basys3板子的串口通信，内容非常纤细，还带有数码管显示(Realization of serial communication of basys3 board)
teacher_uart
- 由verilog编写的uart收发模块，能够在串口助手发送字符，并在数码管上显示，开发板为basys3 内置约束文件(The UART transceiver module written by Verilog can send characters to serial assistant and display them on the digital tube. the development board is built-in constraint file of basys3)
基于basys3的推箱子游戏
- 基于FPGA的游戏实例，开发板为Xilinx的basys3，VGA显示(Basys3, VGA Display of Xilinx Development Board Based on Game Example of FPGA)