搜索资源列表
DE0_Nano_SOPC_DEMO
- Altera DE0-Nano 开发平台SOPC可编程片上系统实现官方Demo。-Altera DE0-Nano development platform the SOPC programmable on-chip system Official Demo.
DE0_NANO_default
- Altera DE0-Nano 开发平台点亮LED基本应用官方Demo。-Altera DE0-Nano development platform lit LED applications Official Demo.
myfirst_niosii
- Altera DE0-Nano 开发平台NiosII软核处理器RSIC。-Altera DE0-Nano development platform NiosII the soft core processor RSIC.
touch-screen
- 基于DE0的触摸屏设计 VHDL 语言 大作业-DE0-based touch-screen design VHDL language major operations
wm8731demo.tar
- wm8731demo de0 iic altera nios-wm8731demo de0 iic altera niosii
Using_the_SDRAM_on_DE0_Board
- Using the SDRAM on Altera’s DE0 Board with VHDL Designs
num_clock
- 基于DE0实验板开发的verilog数字钟程序。实现了12/24小时制切换；闹钟；整点报时等功能。-Based on experimental board development DE0 verilog digital clock procedures. To achieve a 12/24 hour switch alarm clock whole point timekeeping function.
smartWasher
- QUARTER编程环境实现的智能洗衣机系统，通过DE0板子进行模拟，组要完成洗衣机5个步骤的顺序过程以及系统相应动作-QUARTER programming environment of intelligent washing system, through simulation DE0 board, groups 5 to complete the washing process and the system the sequence of steps corresponding action
juzhenjianpan
- 矩阵键盘应用于FPGA的verilog代码，使用的是DE0，引脚已分配-Matrix keyboard used in the FPGA verilog code, using DE0, pin has been assigned
signal_generator_430
- 基于430单片机的与DE0 FPGA 的信号发生器，还有测频、测相、测幅、扫频功能。-Based on 430 single and DE0 FPGA signal generators, as well as frequency measurement, the measured phase, the measured amplitude, sweep function.
CPLD_LCD
- 用verilog编写的1602显示屏的程序，通用性较强，测试平台是DE0-Written in verilog 1602 Display of the program, versatility is strong, the test platform is DE0
ads805
- 电设用到！用verilog编写的TI的ADS805的调试程序。测试平台是DE0 。-Electric facilities used! TI' s written in verilog ADS805 debugger. Test platform is DE0.
vga_cd
- 用verilog编写计数程序，在VGA上显示的，适合VGA的初学者。测试平台DE0 。-Counting program written in verilog, displayed on the VGA, VGA suitable for beginners. Test platform DE0.
Phone-Call-Meters-by-Quartus9.2
- 本次设计主要基于FPGA器件完成了一个IC电话计费器的设计，其能够显示用户IC的卡值余额，并能够根据用户当前的话务种类和通话时间进行扣费，并将用户的实时余额和通话时间通过4位LED七段显示器显示出来。整个设计过程采用自顶向下的分块设计方法，即将整个电话计费系统分为电话计费、计时模块和显示模块两大模块，其各模块的实现是基于QuartusⅡ9.2平台使用DE0硬件描述语言编程实现的。-This design is mainly based FPGA devices completed a telep
vhdl
- altera DE0 fpga开发板中文资料-altera DE0 fpga development board Chinese data
exemplos_em_C_para_pic_16f628acodigofonte
- contador de pulsos de0-99 para pic 16f628 escrito para compilador ccs
DE0_mpu6050_uart_timer
- 基于DE0开发板的MPU6050数据采集，同时使用定时器，同时每一毫秒从串口发送数据，包含Quartus硬件电路部分-DE0 based development board MPU6050 data collection, using a timer, but every millisecond to send data from the serial port, including hardware circuit part Quartus
vga
- DE0 VGA control clk_div, ctrl, pattern
Demonstrations
- DE0 开发板的用户手册（EP3C16F484）实例 verilog-DE0 （EP3C16F484）verilog example
cyclone3_DE0_EP3C16F484handbook
- DE0 开发板的用户手册（EP3C16F484）实例 verilog-DE0 cyclone III EP3C16F484 handbook