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Tracking
- 实现gps卫星的跟踪功能。载波跟踪环采用锁频环辅助下的锁相环，码跟踪环采用延迟锁相环。-Gps satellite tracking to achieve. Carrier tracking loop using the aid of frequency-locked loop PLL, code tracking loop using delay locked loop.
CyclonePLL
- Cyclone™ FPGA具有锁相环（PLL）和全局时钟网络，提供完整的时钟管理方案。Cyclone PLL具有时钟倍频和分频、相位偏移、可编程占空比和外部时钟输出，进行系统级的时钟管理和偏移控制。Altera® Quartus® II软件无需任何外部器件，就可以启用Cyclone PLL和相关功能。本文将介绍如何设计和使用Cyclone PLL功能。 PLL常用于同步内部器件时钟和外部时钟，使内部工作的时钟频率比外部时钟更高，时钟延迟和时钟偏移最小，减小或调整时钟
DDR_SDRAM_controller
- DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides t
thermal_DLL
- gps延迟锁定环中对热噪声的模拟，考虑了热噪声对跟踪精度的影响，很不错的-gps delay locked loop in the thermal noise of the simulation, taking into account thermal noise on the impact of tracking accuracy, very good
video_process_base_on_DSPandFPGA
- 基于高速数字信号处理器(DSP) 和大规模现场可编程门阵列( FPGA) ,成功地研制了小型 化、低功耗的实时视频采集、处理和显示平台. 其中的DSP 负责图像处理,其外围的全部数字逻辑功能都集成在一片FPGA 内,包括高速视频流FIFO、同步时序产生与控制、接口逻辑转换和对视频编/ 解码器进行设置的I2 C 控制核等. 通过增大FIFO 位宽、提高传输带宽,降低了占用EMIF 总线的时间 利用数字延迟锁相环逻辑,提高了显示接口时序控制精度. 系统软件由驱动层、管理层和应用层组成,使得硬件管
wtut_sc
- DCM includes a clock delay locked loop used to minimize clock skew for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices. DCM synchronizes the clock signal at the feedback clock input (CLKFB) to the clock signal at the input clock
ADifferentiallyCoherentDelay-LockedLoopforSpread-S
- 详细讲述了直接序列扩频差分锁相环的文章，包含具体的算法结构，并附有仿真结果。-A novel differentially coherent delay-locked loop(DCDLL) for accurate code tracking is proposed for direct sequence spread spectrum systems. Due to the use of the differential decoder and exactly one correlato
dll_good_2137
- Delay locked loop Exmples
TDTL_zero_order
- 在matlab与SystemGenerator的平台下实现零阶时延数字正切锁相环。此模块最终能达到与输入信号同频率。-In the matlab, and SystemGenerator the platform, zero-order delay tangent digital phase-locked loop. This module is ultimately to reach input signal with the same frequency.
SBOCCrare
- 几个BOC 信号的分析例程，全球卫星导航系统将普遍使用BOC调制信号作为扩频测距信号，BOC信号号自相关函数呈现多个相关峰，传统扩频接收机所用的延迟锁定环（DLL）无法对该信号正确地进行码相位的 -Several BOC signal analysis routines, the global satellite navigation system will generally use the BOC modulation signal as a spread spectrum rangin
Wind
- a new circuit topology of a phase-locked loop that can be used for synchronising a singlephase wind turbine generator (WTG) with the low voltage utility grid. The circuit is based on the time-delay digital tanlock loop (TDTL) architecture and
olpc_dcon
- Load Delay Locked Loop (DLL) settings for clock delay.
thermal_DLL
- gps延迟锁定环中对热噪声的模拟，考虑了热噪声对跟踪精度的影响，很不错的-gps delay locked loop in the thermal noise of the simulation, taking into account thermal noise on the impact of tracking accuracy, very good