搜索资源列表
C64xx_DSP_Cache
- 介绍C64xx DSP Cache的资料，帮助你理解L1，l2的区别-C64xx DSP Cache introductory information to help you understand the L1, l2 distinction
project1_report1
- The purpose of this project is to explore the issues and implementation of a multiple instruction stream, single data stream processor. We are running two instruction streams on two CPUs which share an address space. The processors share a second lev
simulator
- It is a cache simulator for L1 and L2
cache_L2_miss_Tool.tar
- 测量IA32体系cpu中 L2 miss次数的动态库 和 头文件及源代码，适合于研究系统性能研究人员-The dynamic lib is used to get the counter value of L2 miss in IA32 cpu.
cache1
- * This example demonstrates how to switch L2 CACHE mode at run-time. -* This example demonstrates how to switch L2 CACHE mode at run-time.
S5PC100_UM_REV1.04
- Samsung s new ARM cpu datasheet. S5PC100 Spec. - CPU ARM Cortex-A8 667-833Mhz - 32KB L1, 256KB L2 Cache - Video 720p (1280x720 Play. h.264 divx, mp4...) - nand, sd/mmc, usb booting - Windows CE 6.0, Linux (*Android) support - support 1
test
- VS 2008上，测试通过，能过获取CPU的一级数据缓存，以及指令缓存，二级缓存，三级缓存-L1 Data Cache, L2 Cache, L3 Cache
GetCPUL1L2Cache
- 获取CPU一级二级缓存大小 L1 Cache L2Cache-Get CPU L1/L2 cache size (L1 Cache L2Cache)
cache-feroceon-l2
- Feroceon L2 cache controller support driver for Linux.
cache-tauros2
- Tauros2 L2 cache controller support driver for Linux.
cache-feroceon-l2
- Feroceon L2 cache controller support.
mckinley
- Tauros2 L2 cache controller support for Linux v2.13.6.
l2x0
- l2 cache initialization for CSR SiRFprimaII.
cache
- Flush and disable all data caches (dL1, L2, L3.
cache-tauros2
- Tauros2 L2 cache controller support.
bcm1480_l2c
- BCM1280 BCM1480 Board Support Package L2 Cache constants and macros. -BCM1280 BCM1480 Board Support Package L2 Cache constants and macros.
kona_l2_cache
- The aux_val and aux_mask have no effect since L2 cache is already enabled. Pass 0s for aux_val and 1s for aux_mask for default value.
l2cc
- ARM L2 Cache Controller.
l2cache
- If non-0, then initialise the L2 cache prefetch.
suspend-imx6
- sync L2 cache to drain L2 s buffers to DRAM.