搜索资源列表
lfsr
- 伪随机序列产生器－线性反馈移位寄存器，Verilog HDL 原代码。-Pseudo-random sequence generator- linear feedback shift register, Verilog HDL source code.
LFSR
- verilog实现的8阶伪随机序列发生器，文件包含了三种主要模块：控制模块，ROM模块，线性反馈移位寄存器（LFSR）模块。已经通过modelsim仿真验证。-verilog to achieve 8-order pseudo-random sequence generator, the file contains three main modules: control module, ROM modules, a linear feedback shift register (LFSR) mo
lfsr
- 用LSFR实现计数功能，可以减少对寄存器和少一个加法器，涉及verilog的人来说-Used to achieve LSFR counting functions, can be reduced to a few registers and adders, the people involved in Verilog
lfsr.v.tar
- linear feedback shift register for generator in verilog code for random sequence generation.
BIST
- A simple BIST in VHDL. It contains a LFSR with an SISR.
ass1_2_hamming
- Hamming codes are a class of binary linear codes. They can detect up to two simultaneous bit errors, and correct single-bit errors. In particular, a single-error-correcting and double error detecting variant commonly referred to SECDED.-a) Develop a
LFSR_UPDOWN_Verilog
- the LFSR up/down counter are designed in a verilog module easy to implement in any counter operation.
RSN
- “Randomized Smoothing Networks” introduced the idea of using networks composed of a type of comparator/memory element, initialized to random initial states, to create smoothing networks, which take arbitrary input loads into the network and produce a
LAB-16
- 用FPGA实现的性线反馈移位寄存器（LFSR）设计。整个工程在quartusII环境下，用verilog编程。-FPGA implementation of the line feedback shift register (LFSR) design. The whole project in verilog programming the quartusII environment.
CRC32_II
- 基于第二类LFSR串行CRC生成器的32位并行实现结构。用于SATA 3。 verilog语言。-32bit parrallel CRC module as specified in SATA 3. The module is realized with verilog.
lab2B(4)LFSR
- 实现4位二进制随机数的产生的verilog代码(Implementation of generation random 4 bits code in verilog)