搜索资源列表
ram
- 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ens
ref-ddr-sdram-verilog.zip
- sdram的verilog的源码实现,sdram verilog source code realizes
RAM_256x8
- RAM 256x8bits code in VHDL
cpu
- vhdl编的cpu，自己的课程验收实验，微指令实现，流程详细。存储，加减基本运算均有，乘法使用位移相加法得到。其中excel有微程序控制信号的编码，储存ram编写，控制器rom编写等-vhdl code of cpu, its acceptance test program, microcode implementation process in detail. Storage, addition and subtraction are the basic operations, multipl
fifo的vhdl原代码
- 本文为verilog的源代码-In this paper, the source code for Verilog
ram
- ram的vhdl源代码在colloy实现-ram in the vhdl source code to achieve colloy
interleaver
- This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
ram32b
- VHDL code for 32 byte RAM
RAM_Examples
- Verilog hdl code for representing ram and rom "memory" using many methods
RAM
- 用VHDL编写一个字长16位，容量128B的RAM控制实现程序，并进行设计综合和功能模拟 。含源程序，及实验要求。适合初学者学习使用。-VHDL prepared with a 16-bit word length, 128B of the RAM capacity to achieve process control and design of analog integrated and functional. Containing source code, and experimental
RAM
- Code for designing 16 bit RAM
VHDLcodes
- Behavioral descr iption of ALU, RAM MODULE, ROM MODULE, DIVIDE BY N COUNTER, GENERIC DIVIDER 2n+1, GCD CALCULATOR, GCD FSM CODE, JK FLIP FLOP in VHDL . These are fully synthesized codes with optimization.- Behavioral descr iption of ALU, RAM MODULE,
RAM
- Ram with 8 bits implemented in vhdl verilog code
RAM
- ram code in VHDL with its test code
ram
- hi this is ram code in vhdl
fft
- This a vhdl code written to compute fft for the values stored in a RAM. The fft values are stored in bit reversed order finally in the same RAM. Not sure if it is working 100 . For my test input it worked.-This is a vhdl code written to compute fft f
S_ram
- This is code of static ram in vhdl
RAM_BLOCK
- Ram block code in Verilog
vhdl-Language-routine-highlights
- 工程中常用的VHDL控制模块，包括三态门，SDRAM，FIFO，PLL，RAM，FIlter等模块，非常实用的工程代码-Control module of VHDL is commonly used in engineering, including the tri-state gate, SDRAM, FIFO, PLL, RAM, FIlter module, very practical engineering code
ReadWrite-RAM-VHDL-source-code
- This page of VHDL source code covers read RAM and write to RAM vhdl code. RAM stands for Random Access memory.It is a form of data storage for various applications. 1K refers 10 lines used for Address bus (as 2^10=1024) 8 refers Data Bus