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SPWM.rar
- 用cpld开发的关于生成spwm波的vhdl程序代码,Cpld developed by spwm waves on the generation of vhdl code
pwm
- pwm的占空比和死区时间可调的Verilog HDL程序设计和测试-duty cycle of pwm and adjustable dead time of the Verilog HDL design and testing procedures
SPWM
- VHDL采用自然采样法写的SPWM，里面有正弦表，可以通过外接输入正弦波和三角波的频率。 -VHDL using written natural sampling SPWM, there are sine table, you can enter through the external sinusoidal and triangular wave frequency.
FPGAdezizhixingSPWMboChengXu
- 基于FPGA的自治型SPWM波形发生器的设计！正弦脉宽调制（SPWM）技术在以电压源逆变电路为核心的电力电子装置中有着广泛的应用，如何产生SPWM脉冲序列及其实现手段是PWM技术的关键。大家共同探讨哈！-FPGA based SPWM autonomy-based waveform generator design! Sinusoidal pulse width modulation (SPWM) technology in the voltage source inverter circuit
weifenxianxing
- 微分先行pid，c语言程序，平时做实验用的...大家不用编了，希望对大家有用-Difference to pid, c programming language, usually used to experiment ... we do not have compiled, we want to be useful
SPWM
- FPGA上用verilog写的SPWM控制程序，完美运行！自由调试，毕设内容，十分宝贵-The SPWM control program by verilog FPGA perfect run! Free commissioning, Bi-based content, invaluable
SPWMdaima
- spwm算法的verilog实现 对照论文表示成功-spwm algorithm verilog achieve control papers for success
SPWM
- ALTERA FPGA上采用Verilog语言实现查表法产生三电平SPWM-Produce three-level SPWM by look-up table
三角函数的Verilog HDL语言实现
- 以Actel FPGA作为控制核心，通过自然采样法比较1个三角载波和3个相位差为1 200的正弦波，利用Verilog HDL语言实现死区时间可调的SPWM全数字算法，并在Fushion StartKit开发板上实现SPWM全数字算法。(With Actel FPGA as the control core, between 1 and 3 triangular carrier phase difference of 1200 sine wave by natural sampling, rea
SPWM
- 利用verilog语言实现正弦脉宽调制，经过调试可行(Using Verilog language to realize sinusoidal pulse width modulation)