搜索资源列表
Crc_Parallel
- CCITT Parallel CRC 16-bit
ps2.vhd
- vhdl ps2 interface for practical use. please send me a response.
booth_multiplier.vhd
- 这个程序实现了定点整数补码一位乘法运算器-booth_multiplier
FINAL_OUT.VHD
- this is a vhdl program to test your LCD
dianziqin
- 这个程序是利用Quartus II编写的利用数控分频器设计硬件电子琴，主系统由3个模块组成，顶层设计文件内部有三个功能模块：SPEAKER.VHD 和TONE.VHD和NoteTabs.vhd。模块TONE是音阶发生器，模块SPEAKER中的主要电路是一个数控分频器，NOTETABS模块用于产生节拍控制和音阶选择信号。-This program is the use of Quartus II design prepared by the use of CNC divider hardware
sqrt
- This zip file contains the verilog source code for square root calculation and its test bench
7212736-Designing-and-Simulation-of-ALU-Using-VHD
- vhdlprogrammes continues to
vhd
- vhdl课件，基础教程，简单入门，适合初学者学习- useful
VHD
- 时钟输入，寄存器定义，中断定义，中断请求定义。-The clock input, register definition, interrupt definition, the definition of the interrupt request.
taxi-VHD
- 出租车计数器的VHDL编程源码，包含整个工程文件-出租车计数器的VHDL编程源码
uart_vhd
- Test Uart on board Nexys 2by VHD
74LS160
- 源码，VHDL语言编写的74LS160计数器-Source code, VHDL language of the 74LS160 counter
spi_tx
- 关于串口通讯(SPI)的VHDL源程序,可以在通用串口通讯中-On the serial communication (SPI) of the VHDL source code, can be general-purpose serial communication
C_8259.vhd
- 一种简单的C-8259示例程序，为中断控制程序设计提供基础。 -a kind of CONTROLER。
wave2
- eda课程设计:dds信号发生器.vhd原理及过程-failed to translate
3FSK.vhd
- 利用MAXPLUS作为仿真工具，用VHDL语言编程，采用频率键控法实现3FSK调制。对输入的系统时钟分别进行2分频，4分频和8分频得到这3种频率。通过对数字基带信号进行双二进制编码得到3个电平值，把它们作为三选一开关，来分别选择不同的频率值、选择不同的信号，从而实现3FSK调制。-As a simulation tool used MAXPLUS using VHDL language programming, using frequency shift keying modulation me
ALU.vhd
- Desarrollo de la Unidad Légica Aritmética (ALU) en VHDL
counter.vhd__
- counter.vhd- counter.vhd
ADV7180.vhd
- this files describe how to configure an ADV7180
crc_peripheral
- -- crc.vhd -- Used for calculation of CRC16-CCITT -- Intended use is as custom peripheral for Nios processor -- When address is logic 0 => -- Internal CRC register is initialised with write_data value -- When address is logic 1 =>