搜索资源列表
DPLL(VHDL).rar
- 使用VHDL语言进行的数字锁相环的设计,里面有相关的文件,可以使用MUX+PLUS打开,The use of VHDL language of digital phase-locked loop design, there are relevant documents, you can use MUX+ PLUS Open
mux
- 多路选择器 verilog CPLD EPM1270 源代码-MUX source verilog CPLDEPM1270
mux
- 多路选择器是一个多输入,单输出的组合逻辑电路,在算法电路的实现中常用来根据地址码来调度数据。-MUX is a multi-input, single-output combinational logic circuit, in the algorithm used in the realization of circuits to address code in accordance with scheduling data.
Electronic-Design-Automation
- 用vhdl语句描述4位等值比较器,4选1多路选择器,8位奇偶校验电路功能-VHDL language used to describe the equivalent four comparators, 4 election more than one MUX, 8-bit parity circuit functions
mux21a
- 2选1多路选择器的VHDL完整描述,即可以直接综合出实现相应功能的逻辑电路及其功能器件。图6-1是此描述对应的逻辑图或者器件图-2 election more than one MUX complete descr iption of the VHDL, which can be directly integrated to achieve the corresponding function logic devices and their functions. Figure 6-1 is th
mux21
- 一个比较简单的2选1多路选择器,初学者可以借以熟悉软件-A relatively easy one of the 2 election MUX, beginners can be so familiar with the software
mux
- Mulriplexer is implemented using VHDL.
vhdl
- Very high speed integrated Hardware Descr iption Language (VHDL) -是IEEE,工业标准硬件描述语言 -用语言的方式而非图形等方式描述硬件电路 容易修改 容易保存 -特别适合于设计的电路有: 复杂组合逻辑电路,如: -译码器,编码器,加减法器,多路选择器,地址译码 -Very high speed integrated Hardware Descr iption Language (VHDL)-
Inpout32
- 32 bit inout mux for embedded design
mux
- A Mux example written in VHDL.
mux
- VHDL realization of MultiPl
mux
- vhdl code for multiplexer and detemines how multiplexer works
mux2x1
- mux 2x1 designed on vhdl fpga adv. pro
MuxDemux_E1_E3
- E3 -Mux / Demux - Multiplexer of 16 E1 Channels-E3 -Mux / Demux - Multiplexer of 16 E1 Channels
vhdlcodes4
- VHDL coding for 4X1 mux in behavioural modelling and for 16X1 mux in structural modelling.
MUX
- VHDL Code for 4:1,2:1 MUX using when statment
mux16_1
- VHDL code foe 16:1 MUX using structural modelling
MUX
- VHDL code for MUltiplexer
mux
- A multiplexer code in vhdl
4x1_mux
- this a simple Verilog source code for 4X1 mux.-this is a simple Verilog source code for 4X1 mux.