搜索资源列表
VHDLVERILOG
- 含近百个源码的VHDL与Verilog相对照的很不错的资料，内容涵盖了从基本说明到高级设计案例，有很强的实用性，值得一看。-Containing hundreds of VHDL and Verilog source contrast is very good information, which covers from basic instructions to advanced design of the case, there are strong practical, worth a v
vga
- 基于EPM1270的VGA显示器接口源码Verilog-Based on the EPM1270
vga3_you
- VGA 显示的详细完整源码，已验证通过-VGA display the full details of source, has been verified through
REG8
- 寄存器的VHDL源码.可能有点简单 新手大家间量 希望和大家学习-VHDL source register. May be a bit simple volume between novice you would like to learn
auk_ts_input
- ts流输入virilog源码-ts stream input source virilog
cpldbus51
- CPLD与8051的总线接口VHDL源码-CPLD with 8051 bus interface VHDL source
usb_funct
- VHDL USB2.0接口源码,内有说明,详细.-VHDL USB2.0 interface source code, which is described in detail.
c19_CICfilter
- 精通verilog HDL语言编程源码之5--CIC积分梳状滤波器设计-Proficient in verilog HDL source language programming of 5- CIC Integrator Comb Filter Design
c20_cordic_computer
- 精通verilog HDL语言编程源码之6--CORDIC数字计算机的设计-Proficient in language programming verilog HDL source of 6- CORDIC digital computer design
c23_RS_decoder
- 精通verilog HDL语言编程源码9——RS(204,188)译码器的设计-Proficient in verilog HDL source programming language 9- RS (204188) decoder design
miniUART
- 自适应波特率的通用异步串行接口电路（ＵＡＲＴ）的ＶＨＤＬ源码，在ＡＬＴＥＲＡ上运行成功-Adaptive baud rate of the universal asynchronous serial interface circuit (UART) the VHDL source code, to run successfully in ALTERA
dff
- 用vhdl编写的D触发器，锁存器等，不需帐号就可自由下载此源码-VHDL prepared using D flip-flops, latches and so on, no account can be a free download this source
divider
- 该模块为分频器，将1KHZ的时钟频率分频成每分钟一次的时钟频率 事实上，该源码可以实现任意整数的分频，主要让N的值设置好相应的数字-The module for the divider, the clock frequency 1KHz frequency per minute into the first clock frequency In fact, the source can be any integer frequency, mainly to allow the value o
cpu01
- 一个简单的cpu的VHDL源码描述，希望对大家有点用呀-Cpu a simple descr iption of the VHDL source code, I hope all of you a bit with it
juanjiqi
- 这是一个卷积器的设计，源码值得好好地学习-This is a convolution design, source code should be a good learning
vhdl_source
- 硬件编写语言，很多VHDL源码例程，纯文本，可直接用在工程中-Hardware language, VHDL source code a lot of routines, plain text, can be directly used in engineering
VHDLjiaotongdeng
- 有关毕业设计交通灯的ＶＨＤＬ设计，包括源码程序和仿真图形相关报告。-Traffic lights on the graduation project of VHDL design, including source code and simulation procedures related to the report graphics.
digital_filter
- 数字滤波器VHDL源码，在matlab下仿真-Digital filter VHDL source code, under the simulation in matlab
risc
- 嵌入式risc处理器源码，包含设计文档，原理图，testbench，及外围接口，使用verilog实现。-Source embedded RISC processors, including design documents, schematics, testbench, and peripheral interfaces, the use of Verilog to achieve.
classic_Verilog_135_examples
- Verilog的135个经典设计实例。包含源码和说明-Verilog of 135 examples of classic design. Contains the source and descr iption