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fenpin
- 利用verilog语言，设计分频器，很不错的参考资料
半整数分频器的实现（verilog）
- 半整数分频器的实现（verilog），本文以6.5分频为例！很实用的！,fen pin qi
FPGA-verilog-fenpin
- FPGA最常用的功能，分频，利用verilog HDL语言实现的，非常适合初学者。-FPGA most commonly used functions, frequency, using verilog HDL language, and is ideal for beginners.
fenpin
- 介绍几种常见的verilog语言的分频方法的文档-Describes several common methods of verilog language document frequency
fenpin
- 开发工具是quartus II 7.0以上版本，这是一个verilog语言的分频器设计，个人作业设计，供参考学习-verilog，quartus II 7.0
fenpin
- verilog语言编写的分频程序，可以通过defpram实现任意整数任意占空比分频，有详细注释-divider verilog language program can be achieved through defpram arbitrary integer divide any duty, detailed notes
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- Verilog 实现任意占空比、任意分频的方法-Verilog achieve any duty, any method of dividing
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- 这是一个二进制的最简单分频器，是一个简短的fpga代码，用verilog书写-This is the most simple of a binary frequency divider, the fpga is a short code, written in verilog
fenpin
- 这个是简单的ppga的verilog的实例。入门着可以看看。-This is an example of a simple ppga of verilog. Getting a look at.
fenpin
- 用verilog HDL编写的任意数分频，包括偶数分频和奇数分频等。-The any number of points, including even frequency and odd frequency, etc..using Verilog HDL
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- 任意分频VERILOG实现，包括奇数分频、偶数分频，与小数分频等等。-Arbitrary frequency VERILOG implementation, including the odd frequency, even frequency, and fractional frequency division, etc..
fenpin
- 可以实现n+0.5倍的分频，本程序是利用50MHz的FPGA开发板实现分别实现10MHz，2.5MHz的分频时钟。(N+0.5 times can be achieved frequency division, this procedure is to use 50MHz FPGA development board to achieve, respectively, 10MHz, 2.5MHz frequency division clock.)
fenpin
- 实现奇数、偶数分频,fpga,Verilog,时钟分频(clock divider,frequency division)
fenpin
- 用verilog语言设计了一个分频器，晶振频率为50MHz(A frequency divider is designed in Verilog language. The frequency of crystal oscillator is 50MHz)