ahb sdram interface.arm cpu series,include controller

开源的基于SystemC的模拟器，可以模拟ARM CPU, Cache, DDR，NOR, NAND, 时序和功耗均可以正确模拟。-This simulator is a cycle-accurate system-level energy and timing simulator. Developed by Embedded Low-Power Laboratory, Seoul National University. The simulator’s underlying kernel is

Single Data Rate Mobile SDRAM Controller Core with AHB Interface

基于AMBA总线的DDR2 SDRAM控制器研究与实现-AMBA bus-based Research and Implementation of DDR2 SDRAM Controller