搜索资源列表
ppt
- 介绍 AXI 协议的PPT, 和一个 slave（verilog实现） 接口的简单实现，需要的可以看看；-AXI protocol described PPT, and a slave interface is simple to achieve, need to look at
handshake
- AMBA 3 AXI handshake protocol. Verilog platform. master and slave.
BP062-BU-01000-r0p0-00rel0[1][1].tar
- AXI协议检查器，由ARM公司开发对于想开发AXI master和slave模型的ASIC设计人员非常有用！-AXI protocol checker, developed by ARM to develop for the AXI master and slave model is very useful ASIC designers!
eetop[1].cn_axibusregslice
- axi总线读写通道插入一级寄存器模块verilog源码,已验证- a slave interface is simple to achieve, need to look at
src
- AXI Slave codes in verilog. Downloded from www.opencores.org free download
AXI_slave
- 自己写的 AXI slave 代码，是ARM 内嵌的 总线通信-AXI slave code
AXI slave
- 使用verilog语言实现了AXI总线通信协议的从机部分(The slave part of AXI bus communication protocol is realized by using Verilog language)
slave
- xilinx Zynq 中的AXI总线 axi slaver模块(AXI bus Axi slaver module in Xilinx Zynq)
axi_slave
- amba总线中axi的slave部分，用verilog实现的slave.(The slave part of Axi in the AMBA bus, slave. implemented with Verilog)
new.v
- 状态机写的axi slave，模式较少，基本功能齐全，轻便,仿真综合通过(AXI4 slave programmed by state machine approach)
axi slave model
- axi slave model,verilog源码
AXI slave
- AXI slave 完整 verilog代码。测试验证通过。