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viterbi_for_bch.rar
- Viterbi based trellis decoder for (7,4) - binary BCH code,Viterbi based trellis decoder for (7,4)- binary BCH code
BCH_Decoder72
- BCH代码,采用VHDL实现,能够实现纠错,带有波形。-BCH code, the use of VHDL implementation, be able to achieve error correction with waveform.
Verilog_for_BCH
- 使用verilog语言实现BCH编码,用于通信信道编码-Using verilog language implementation BCH coding, channel coding for communication
BCHbch
- BCH编码 实现BCH信道编码功能 实现BCH信道编码功能-BCH code BCH code BCH code BCH code BCH code BCH code BCH code
rs_encode
- 这是用verilog编写的RS(204,188)代码,适用于数字电视的BCH编码过程。-This is the verilog prepared using RS (204,188) code, the application of digital television in the course of the BCH code.
bch_encode
- this bch encoder verilog code-this is bch encoder verilog code
BCH[31-16]-with-BPSK-MFSK
- comperation of performance of BCH [31 16] code with BPSK and MFSK
BCH_EN
- 基于FPGA的GPS/BD信号发生器中BCH编码发生器模块,使用verilog编写- FPGA-based GPS/BD signal generator BCH code generator module, using verilog write
BCH_VLSI
- 使用HLS完成BCH编码的运算通路的设计,纯组合逻辑,对于65nm工艺可跑上1GHz。已经组合逻辑分为了多个部分,可在每一个部分之间插流水线。 附上可综合的纯RTL Code以及C++代码,以及Modelsim仿真。 可通过我的优化选项来学习如何优化HLS工具生产的代码。(BCH Encoder realized using HLS tool. Combinational logic.)
bch_verilog-master
- BCH code Open Source
2bit_ecc
- 基于BCH码的ECC纠错算法,可纠错2位错误码,供参考(Based on BCH code ECC error correction algorithm, two error codes can be corrected for reference.)