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divider.8位的除法器
- 8位的除法器。用VHDL语言进行设计实现。,8-bit divider. With VHDL design languages.
div(FLP).rar
- 是Nios II處理器下客製化指令的一個32位元浮點數除法器，可將兩IEEE 754格式的值進行相除,Nios II processors are customized instruction under a 32-bit floating-point divider can be two format IEEE 754 value division
32bit.zip
- multiplier and divider verilog codes,multiplier and divider verilog codes
32_16div
- 这是一个简单的除法器（32bit/16bit),采用移位相减法-This is a simple divider (32bit/16bit), using phase shift subtraction
divider
- 16位有符号整数除法，将商并入移位后的被除数，节省资源。-16-bit signed integer division, will shift into business after the dividend, saving resources.
divide
- It is n-bit sequential divider in verilog language
HG_chufaqi_clajiafaqi
- VHDL基-16位的无符号除法器，超前进位加法器可改位数。-VHDL-based-16 bit unsigned divider, CLA can be the median.
f_divider
- 16-bit frequency divider (32 MHz,16,8,...) based on altera fpga.
division1
- 基于vhdl/verilog的18位除法器程序。已经过仿真和综合。-Based on vhdl/verilog program for 18-bit divider. Has been simulation and synthesis.
div_8
- 八位除法器 VHDL实现 八位除法器 VHDL实现-8-Bit divider 8-Bit divider 8-Bit divider
Chapter11-13
- 第十一章到第十三章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个
2
- 介绍一种软件实现分频器和32位计数器，采用可编程逻辑芯片，运用verilog语言设计出一种分频器和32位计数器 -Introduce a software implementation of divider and 32-bit counter, using programmable logic chips, using verilog language to design a divider and 32-bit counter
5956447divider
- 基于srt-2算法，利用verilog实现16位定点无符号数除法器（除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成）-Based on srt-2 algorithm, using verilog to achieve 16-bit fixed-point unsigned divider (divisor, dividend by 16-bit integer and 16-bit decimal form, business from the
fpga_chufaqi
- 基于fpga的32位除法器的设计，开发环境vhdl-Fpga-based 32-bit divider design, development environment vhdl
divider
- 用VERILOG实现一个被除数为8位、除数为4位的高效除法器-With VERILOG implement a dividend for the 8-bit, 4-bit effective divisor divider
VHDL
- 除法器 4位除法器 可以编程实现 有启发意义-4-bit divider divider can be programmed instructive
deccount16nr
- 16位任意计数分频器,VHDL语言实现,通过测试-Any count 16-bit divider, VHDL language
16_fenpinqi
- 这是一个用VHDL语言实现的16位分频器，能够实现分频作用，是一个完整的代码，大家可以参详参详。-This is a VHDL language with 16-bit divider, frequency effects can be achieved, is a complete code, we can participate in detailed reference.
12
- 4位除法器 library IEEE use IEEE.std_logic_1164.all use IEEE.std_logic_unsigned.all entity fpdiv is port ( DIVz: out STD_LOGIC A: in STD_LOGIC_VECTOR (3 downto 0) B: in STD_LOGIC_VECTOR (3 downto 0) data_out: out STD_LO
divider
- FPGA除法器的使用32位的，有商和余数-FPGA using 32-bit divider, there are the quotient and remainder