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P4_PPC_SDRAM_Reference_Design
- SDRAM 参考设计:主要包括The following figure shows a high-level block diagram for this reference design followed by a brief descr iption of each sub-section. The design consists of: · PowerPC processor · PLB-OPB bridge · BlockRAM Memory Controller ·
BlockRAM
- xilinx BlockRAM 级联，利用Xilinx原语（非IP Core），更大灵活性-xilinx BlockRAM cascade, using Xilinx primitive (non-IP Core), greater flexibility
blockram
- 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
fifo_src
- verilog语言实现，利用BlockRAM实现FIFO。-Verilog language, the use of BlockRAM achieve FIFO.
shift_regeister
- 用blockram实现移位寄存器，开发语言为verilog hdl-Shift register with blockram achieve the development language for the verilog hdl
BlockRam
- xilinx FPGA BlockRam source.
BlockRam
- 块状ram使用实例，实现深度和宽度可调的FIFO，buffer。-The block ram instance, depth and width adjustable FIFO, buffer.
ramIPcore
- 基于quartusII的ram调用，利用FPGA自身的blockram创立ram的ip core-Based on the ram quartusII calls itself blockram created using FPGA ram' s ip core
ug480-ver1.5
- 利用实验板上的XADC资源，对芯片温度、内部电源进行定时采集和监控，并把信息存入blockram,可实现翻看，并有按键消抖模块-XADC resource use experimental board, the chip temperature, the internal power supply timing collection and monitoring, and put information into blockram, look can be achieved, and a key
bram_shift_reg_w16x3072
- 使用 xilinx blockram 做连续shift 在图像处理中 做多行缓存很方便-Using blockram Xilinx as a continuous shift in the image processing to do more than the cache is convenient
utosnet_latest.tar
- The uTosNet framework aims at providing a very fast method for interfacing physical components, such as motor drivers, ADCs, encoders, and similar, to applications on a PC. The framework is based on the Node-on-Chip architecture (link to paper comi
pg058-blk-mem-gen
- blockram的手册，适合开发者使用是xilinx的(Blockram manual, suitable for developers to use, is Xilinx)