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1下载：
基于FPGA的CAN总线控制器，VERILOGHDL源代码，Q2仿真实现。可用。-FPGA-based CAN Bus Controller, VERILOGHDL source code, Q2 Simulation. Available.
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已经验证可用。此代码为Verilog写的sdram的控制器，可以由用户的使用而加载到自己的项目中自行开发。,Have verified that is available. This Verilog code written sdram controller, can be loaded into the user' s use of their own self-developed projects.
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这是CAN总线控制器的IP核，源码是由Verilog HDL编写的。其硬件结构与SJA1000类似，满足CAN2.0B协议。,This is a IP core of the CAN bus controller written by the Verilog HDL. whose structure is similar with SJA1000,supporting the protocol of CAN2.0B.
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第十章的代码。
本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相
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DDR3控制器，基于Altera平台，修改管教后直接可以下载进PFGA-DDR3 controller, based on Altera platform, modify the discipline can be downloaded directly into the PFGA
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第六章到第九章的代码
本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
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一个LCD控制器的verilog源代码，可以方便的控制TFT LCD！-An LCD controller Verilog source code, can easily control TFT LCD!
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can控制器IP核，verilog语言描述实现。含测试例-can controller IP core, verilog language described realize. Containing the test cases
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GPIO (General Purpose Input and Output ports) with microprocessor programmable tri-state bus interface-Use verilog to design a 48 control points that can be programmed to input or output controller
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Verilog 下脉冲发生器的源代码，可用于模拟三相交流电过零点，主要用于调试一些类似SVC（无功补偿）控制器的一些算法-Pulse generator under the Verilog source code, can be used to simulate three-phase alternating current zero-crossing point, mainly for debugging similar SVC (reactive power compensation) co
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verilog code for can controller
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基于Verilog+HDL设计CAN控制器,详细介绍各功能模块的设计。本论文的重点是CAN总线通信控制器的前端设计。即用Verilog HDL语言完成CAN协议的数据链路层的RTL级设计，实现其功能，并且能够在FPGA开发平台Quartos上通过仿真验证，证明其正确性-Verilog+ HDL-based design of CAN controller, detailed design of each functional module. This paper focuses on the C
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USB控制器的VERILOG工程文件，工程为ISE的，可以编译通过，压箱底的东西了-USB controller VERILOG project file, works for the ISE, you can compile, pressure bottom of things
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使用verilog语言实现的CAN控制器代码。-Use the CAN controller verilog language code.
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verilog hdl 语 言 实 现 的 CAN 控 制 器-CAN controller verilog hdl language
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CAN控制器源码 Verilog-CAN controller source Verilog
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can协议转换控制器的Verilog代码，在Quartus软件上测试通过-The CAN protocol conversion controller Verilog code, through the test on Quartus software
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This SDRAM controller is useful for SDR_SDRAM IC's can be integrated with the verilog code. The code is developed for the altera FPGA's and it can be ported to other FPGA's easily. The code is verified with terasic DE2-115 board and DE2 boards.
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Introduction
Synchronous DRAMs have become the memory standard in many designs. They provide substantial advances in
DRAM performance. They synchronously burst data at clock speeds presently up to 143MHz. They also provide
hidden precharge time and t
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实现了can控制器Verilog编程使用niosII 开发平台(Can controller Verilog programming, the use of niosII development platform)
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