用Verilog实现卷积码（2，1，2）的编码器，采用状态机来完成在modelsim下的仿真-Verilog implementation using convolution code (2,1,2) encoder, using a state machine to complete the modelsim simulation under the

本代码用VHDL实现了复数的卷积，也许对你会有用-this code written by VHDL completes the convolution of complex numbers,which may be quite helpful to you.