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dcm
- 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
DCM
- ISE实现DCM组建例化，得到3倍频时钟-ISE to achieve established cases of DCM, received 3 octave clock
DCM
- Xilinx公司诸多型号开发版中的一个模块，能够实现1到16次倍频和分频等功能。使用时现在ISE集成开发环境下利用VHDL进行例化。本文档为个人学习总结-Xilinx, a number of models developed version of a module, be able to achieve 1-16 times multiplier and divider functions. ISE now use integrated development environment for
DDR_SDRAM_controller
- DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides t
BUFG_CLK2X_FB_SUBM
- xilinx DCM 应用的源代码，完全可用-xilinx DCM application source code, fully available
xapp462_vhdl
- a example -Code for DCM in language VHDL-a example-Code for DCM in language VHDL
wtut_sc
- DCM includes a clock delay locked loop used to minimize clock skew for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices. DCM synchronizes the clock signal at the feedback clock input (CLKFB) to the clock signal at the input clock
DCM_24M_20M_2M
- DCM实现24M 20M 2Mhz的输出-dcm、 verlig HDL、
Xilinx_DCM
- 基于ise 10.0来实现Xilinx的时钟设计和管理-Xilinx dcm digital clock manager
ledvhd
- ISE与VHDL入门程序，使用DCM分频实现LED的控制。-ISE and VHDL entry procedures with DCM divide LED control.