搜索资源列表
shift
- E1接收部分主要功能是实现从输入的差分线路数据中恢复出2.048M线路时钟并将数据解码输出。包括解码和线路时钟恢复两模块。-E1 to receive some of the major functions of the difference from the input data lines to recover a clock and data lines 2.048M decoder output. Including decoding and clock recovery circuit
E1_Galileo_signal
- The E1 Galileo signal，a PPT ,very good materials about the Galileo signal of eht E1 frequency
AZ324M-E1datasheet
- AZ324M-E1 datasheet.pdf
T1E1
- T1/E1 encoder in LabVIEW
prj
- bitfiles for T1/E1 analis in fpga
E1framerDeframer
- e1 framer and defremerr vhdl cods
E1
- 在国际标准组织开放式系统互联（OSI）参考模型下，以太网是第二层协议。10G以太网使用ＩＥＥＥ（电气与电子工程师学会）802.3以太网介质访问控制协议（ＭＡＣ）、ＩＥＥＥ 802.3以太网帧格式以及ＩＥＥＥ 802.3最小和最大帧尺寸。-In the International Standards Organization Open Systems Interconnect (OSI) reference model, Ethernet is the second-layer protocol.
e1framer_latest.tar
- e1-framer for developing E-1 modems
e1
- 这是一个新兴编程语言“易语言”的视频教程。-This is a new programming language " easy language" of video tutorials.
HDLC_E1
- E1到HDLC转换 实现E1到以太网 E1到HDLC转换 实现E1到以太网-E1 TO HDLC E1 TO ETHETH
E1Tsi_TB
- TSI testbench for E1
E1_to_e3_v.2.1
- E1信号到E3复用解复用VHDL代码包括时钟合成-E1 to E3 multiplexing & demultiplexing VHDL code, ，including clock synthesis
muxdemux_4E1(E2)_to_1E2(E3)
- framer Deframer core multiplexed 4 E1(E2)channel s to one E2(E3) stream at 8.448Mbps(34.368Mbps) rate .
e1framerdeframer
- E1 Framer/De-Framer, Also include the data check (CRC) and channel coding/decoding-E1 framer and deframer, clock adjust, clock phase adjust
e1_framer
- E1 DeFramer :A design for Framing Telecom E1 Interface
e1
- exp-1: To observe the BER performance of a BPSK system in AWGN channel.- exp-1: To observe the BER performance of a BPSK system in AWGN channel.
XAPP868
- E1/T1时钟提取和恢复源码 是xilinx的IP源码-E1/T1 clock recover code,it is xilinx s IP code
234234234
- 基于嵌入式系统的E1以太网桥接器的设计与实现.pdf-the design of E1 ethernet based on emmbedded system
E1
- 分析帧同步算法，提供帧同步的状态机实现图以及得到的正确仿真图形。-Analysis of frame synchronization algorithm, to provide frame synchronization state machine implementation plans and get the correct simulation graphics.
PCK_CRC4_D4
- E1成帧模块，使用VHDL语言设计中的CRC4校验码生成模块-E1 framing module, using the VHDL language design CRC4 check code generation module