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  1. equlizer

    0下载:
  2. 数字均衡器是通讯信道抗码间干扰的重要环节,这是一个用vhdl写的代码以及用SYNPLIFY8.0综合的RTL电路图 它包含三个模块FILTER,ERR_DECISION,ADJUST 希望对大家有用.-equalizer communications channel anti-inter-symbol interference an important link This is a use of the VHDL code to write and use SYNPLIFY8.0 integra
  3. 所属分类:VHDL编程

    • 发布日期:2008-10-13
    • 文件大小:23727
    • 提供者:陈为
  1. DLMS

    0下载:
  2. DLMS equalizer for qam
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-01
    • 文件大小:3378
    • 提供者:cyberia
  1. equizer

    0下载:
  2. HART协议的均衡器设计 DCT LMS 设计 + 位同步设计,仿真证明了设计的有效性-HART protocol design DCT LMS equalizer design+ Bit synchronous design, simulation proves the validity of the design
  3. 所属分类:matlab

    • 发布日期:2017-03-28
    • 文件大小:22270
    • 提供者:进正化
  1. adaptive_lms_equalizer_latest.tar

    0下载:
  2. In communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear. and more sevear is such distortion is random.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-16
    • 文件大小:13862
    • 提供者:Arun
  1. rls

    1下载:
  2. 是二阶RLS自适应均衡的实现,采用V—LOG编写而成,是从工程中截取的 可以直接应用-Second-order RLS adaptive equalizer is the realization of the use of V-LOG prepared is intercepted from the project can be applied directly
  3. 所属分类:Special Effects

    • 发布日期:2017-04-01
    • 文件大小:4957
    • 提供者:刘伟
  1. Adaptive_FIR_Equalizer_With_Continuous-Time_Wide-

    0下载:
  2. Adaptive FIR Equalizer With Continuous-Time Wide-Bandwidth Delay Line
  3. 所属分类:Mathimatics-Numerical algorithms

    • 发布日期:2017-05-11
    • 文件大小:2060843
    • 提供者:asia
  1. Channel_Equalizer

    0下载:
  2. 802.11a接收机的信道均衡源码,verilog语言的-802.11a receiver channel equalizer source, verilog language
  3. 所属分类:3G develop

    • 发布日期:2017-03-31
    • 文件大小:226041
    • 提供者:zhaohaishun
  1. fir_9222_sopc

    0下载:
  2. 基于sopc技术的数字均衡器带通滤波器及12864液晶显示-Sopc technology-based digital equalizer band-pass filter and liquid crystal display 12864
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-20
    • 文件大小:5911361
    • 提供者:z
  1. IterativeDecodingofBinary

    0下载:
  2. In this paper, energy efficient VLSI architectures for linear turbo equalization are studied. Linear turbo equalizers exhibit dramatic bit error rate (BER) improvement over conventional equalizers by enabling a form of joint equalization and deco
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-03
    • 文件大小:1515947
    • 提供者:suresh
  1. VerilogLangRefManual

    0下载:
  2. Simulation results show that energy savings in the range 30–60 and 10–60 are achieved in equalization and decoding, respectively. Furthermore, we present finite precision requirements of the linear turbo equalizer and an efficient rescaling metho
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-03
    • 文件大小:1283063
    • 提供者:suresh
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