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FIFO_Syn
- 同步FIFO功能,verilog语言描述,通过了modelsim 6.0 仿真,Quartue综合
4VerilogFIFO
- 一种新的FIFO实现方法,verilog描述,通过modelsim 6.0 仿真,Quartue综合
FIFO-DC
- FIFO的Verilog程序 已在modelsim中编译通过 并且可以通过DC进行综合
ram_fifo_ram
- 程序实现了在FPGA内部开辟RAM+FIFO+RAM的IP核进行数据之间的调试。方便需要用到的童鞋进行参考。已通过modelsim调试-Implemented within the FPGA program to open up RAM+ FIFO+ RAM for data between the IP core debugging. Need to use the shoes for easy reference. Has passed debug modelsim
fifo
- 异步fifo,用Verilog编写,包含testbench,已经通过modelsim调试,内含文档和波形图-Asynchronous fifo, to prepare to use Verilog, including testbench, debug modelsim has passed, including documents and wave
FIFO
- it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.-it is a
fifo
- 高性能设计中常用的fifo模型,采用单端读取数据的方式,数据的位宽以及fifo的深度可以设置。通过modelsim仿真-Fifo design commonly used in high-performance models, using single-ended way to read data, the data bit width and the depth of the fifo can be set. Modelsim simulation by
fifo_syn
- 同步fifo,有测试向量,用modelsim仿真验证通过。-Synchronous fifo, there are test vectors, by using modelsim simulation.
3fifo_fifo
- 程序实现了FPGA内部FIFO之间的数据传输。已通过modelsim调试!-Procedures to achieve the data transmission between the FPGA internal FIFO. Modelsim has passed debugging!
FIFO_TD
- FIFO的VHDL测试程序,在Modelsim下完全可以运行-The test_bench of fifo
fifo
- 本文档是一个异步FIFO设计的完整工程,利用modelsim仿真软件,分不同的模块-This document is the complete works of an asynchronous FIFO design, the use of the modelsim simulation software, divided into different modules
FIFO
- 将ROM的正弦波数据输入FIFO存储器,然后输出,有modelsim仿真波形-Verilog FIFO ROM mif sine
fifo2
- 异步fifo 先进先出 用于缓冲数据,用verilog HDL所写,在quartus II中测试通过,modelsim仿真-Asynchronous fifo FIFO for buffering data, using verilog HDL written in quartus II test through, modelsim simulation
FIFO1
- 给出一个位宽16比特,深度为10的异步FIFO的设计,并要求给出空或满的指示信号。要求用Verilog HDL语言设计,并编写测试激励,以及用Modelsim进行功能仿真,验证设计正确性。10个16位的数据 (FIFO的宽度:也就是英文资料里常看到的THE WIDTH,它指的是FIFO一次读写操作的数据位,就像MCU有8位和16位,ARM 32位等等。FIFO的深度:THE DEEPTH,它指的是FIFO可以存储多少个N位的数据(如果宽度为N)。如一个8位的FIFO,若深度为8,它可以
FIFO
- 同步时钟FIFO已经在FPGA及modelsim中充分验证-Synchronous FIFO has been fully validated
sobel
- 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测,工程文件可在quartus13.1以上版本打开;工程使用到ram、fifo、pll三种ip核,design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块,sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果;测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化,再将生成文件中数据用串口发给FPGA,边缘检测结果会通过VGA输出。(Written by Ve