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用单片机汇编语言写的使用的子程序 包扩浮点书的加减还有 模糊算法-SCM assembly language used to write the use of the subroutine package expanding the floating-point addition and subtraction algorithm still fuzzy
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verilog编写的32位浮点加法器-32-bit Floating Point Addition Written in Verilog
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CAN总线的FPGA实现，用Verilog编写，代码完整，而且有很完善的测试代码，用ISE直接打开，学习FPGA进阶的好项目-CAN Bus FPGA, written with Verilog, code integrity, but also very good test code, using ISE directly open, a good project to learn advanced FPGA
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介绍一组浮点数的运算代码，包括加减乘除运算的VHDL代码实现-Introduced a set of floating-point code of the operation, including addition and subtraction multiplication and division operations to achieve the VHDL code
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用c编写的用于测试浮点运算峰值的小程序。采用长度为N的浮点数组source[]自身相加N次的方法进行N*N次浮点加法运算来测试浮点加法峰值。-With c prepared for testing small peak floating-point operations procedures. Length of the floating-point numbers for the N group source [] the sum of N times its own methods of N
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一种用VHDL语言描述的浮点除前规格化的源代码编程-VHDL language used to describe a floating-point addition to the source code before the standardized programming
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浮点加减运算的后规格化VHDL程序源代码，很不错，希望对大家有用-Floating-point addition and subtraction operations after the standardized VHDL source code, it is good, I hope all of you a useful
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科学计算器。可以解读表达式，进行整数、浮点数的加减乘除运算。-Scientific calculator. Expression can be interpreted, for integer, floating-point addition and subtraction, multiplication and division calculations.
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产生浮点加法运算单元的测试激励及期望输出-Floating-point addition operations generate unit test incentives and the desired output
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用java实现的逻辑运算程序，可以完成加减乘除和浮点数的表示-Using java process to achieve the logic operations can be completed by the floating-point addition and subtraction and that multiplication and division
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用凌阳单片机61板编程计算器程序。可实现8位数的整数、浮点数的加减乘除计算。-Sunplus board with 61 single-chip calculator programming procedures. Can be 8-digit integer, floating-point addition and subtraction, multiplication and division calculation.
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浮点运算加减乘除四则运算，方法和特别，值得借鉴-Four floating-point addition and subtraction multiplication and division operations, methods, and in particular, it is worth drawing
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Floating point addition assembler in MIPS
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能够实现定点小数的机器数表示、定点小数的变形补码加减运算、定点小数的原码一位乘法运算和浮点数的加减运算。-Able to achieve fixed-point decimal number of machines that the deformation of complement fixed-point decimal addition and subtraction operations, the original code a fixed-point decimal multiplica
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verilog写的浮点运算加法，希望对大家有用处-verilog to write floating point addition, we want to be useful
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Simple floating point addition unit written in Verilog
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建议计算器，能进行浮点数的加减乘除，swing界面-Recommended calculator for floating-point addition and subtraction, multiplication and division can, swing interface
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浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmab
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浮点数的加法，基于vhdl语言实现，在电机控制中经常使用-Floating point addition, based on vhdl language, often used in motor control
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Arithmetic and logic unit for floating point single precision addition/substruction, multiplication, division and square root.
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