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verilog 128位 突发4. sdr fpga控制器
- verilog 128位 突发4. sdr fpga控制器,verilog 128 bit unexpected 4. sdr fpga controller
(fpga)sdram.rar
- verilog 代码，读写SDRAM 不带仿真，需要自己编写测试文件,Verilog code, read and write SDRAM simulation without the need to prepare their own test documentation
FPGA_SDRAM_PCI
- 一个基于FPGA的PCI数据采集程序，包括SDRAM控制，PCI9054时序控制，开发语言verilog，开发环境quartus-FPGA-based PCI data acquisition procedures, including SDRAM control, PCI9054 timing control, the development of language verilog, development environment quartusII
sdr_c_trl_verilog
- SDRAM 控制器的Verilog代码 经过综合验证过的.无截压密码-SDRAM controller Verilog code comprehensive test after all. No cut-off pressure Password
AlteraSDR-SDRAM
- Altera 官方提供的SDRAM控制器,verilog的-SDRAM controller provided by Altera in Verilog HDL
webCam-FPGA
- 使用Verilog控制美光CMOS图像处理器，并转存到SDRAM中。使用FPGA为QL的带fuse系列-Control the use of Verilog Micron CMOS image processor and SDRAM in转存到. FPGA for use with QL series fuse
FPGAbasedSDRAMControll
- 基于FPGA的SDRAM控制器 Realization FPGA-based SDRAM Controller with Verilog-FPGA-based SDRAM Controller Realization FPGA-based SDRAM Controller with Verilog
sdram_vhd_134
- This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory. This code is Verilog. This code is based Xilinx FPGA Playform.
c_xapp260
- xilinx应用指南xapp260的中文翻译版本。利用 Xilinx FPGA 和存储器接口生成器简化存储器接口。本白皮书讨论各种存储器接口控制器设计所面临的挑战和 Xilinx 的解决方案，同时也说明如何使用 Xilinx软件工具和经过硬件验证的参考设计来为您自己的应用（从低成本的 DDR SDRAM 应用到像 667 Mb/sDDR2 SDRAM 这样的更高性能接口）设计完整的存储器接口解决方案。-The use of Xilinx FPGA and Memory Interface Gen
median
- 中值滤波的实现，该代码使用的是verilog 语言 module median(clk,reset,load,din,mult,dout,over,a3,b3,c3,a2,b2,c2,a1,b1,c1)-Median filter implementation, the code using verilog language module median (clk, reset, load, din, mult, dout, over, a3, b3, c3, a2, b2, c2, a1,
Verilog-DRAM
- fpga(veriloh hdl)编写的SDRAM程序说明 -fpga(veriloh hdl)SDRAM
sdram
- 用verilog语言编程实现的SDRAM模块，可用于配置在FPGA中-Verilog language programming with the SDRAM module, can be used to configure the FPGA,
FPGA_SDRAM
- FPGA对SDRAM的控制操作源码,用VERILOG硬件描述语言编写,包含的文件一共有:hostcont.v,inc.h,pinouts.ucf,sdram.v,top.v,tst_inc.h-Control of operation of the SDRAM FPGA source code, using VERILOG hardware descr iption language, the file contains a total of: hostcont.v, inc.h, pinout
SDRAM
- FPGA SDRAM控制器Verilog源码，通过测试-FPGA SDRAM VERILOG
sdram_mdl
- verilog编写的对SDRAM的控制的源代码，开发FPGA/CPLD-verilog SDRAM write control of the source code, development FPGA/CPLD
controller-design-of-sdram-
- 基于FPGA对sdram控制器的设计（VERILOG语言）-FPGA-based controller design of sdram (VERILOG language)
SDRAM_verilog-serial-port
- FPGA对sdramd的操作，verilog语言设计！-FPGA SDRAM verilog
sdram-ctrl
- FPGA sdram 全页模式控制，用verilog语言写的，非常的精简，控制方便-FPGA sdram full-page mode control, written in verilog language is compact, easy to control
SDRAM
- 基于fpga与verilog语言的的sdram读写(SDRAM reading and writing based on FPGA and Verilog language)
sdram
- sdram的驱动开发，支持单字节读写，全页读写，自定义长度读写。(SDRAM drive development, support single byte read and write, full page read and write, custom length read and write.)