搜索资源列表
I2C-in-CPLD
- I2C在CPLD上的模拟实现源程序,用C语言编写而成-I2C CPLD in the simulation source code, C language prepared! !
i2c
- SAA7114 和 FPGA/CPLD之间通讯的程序,本人觉得比较好,而且里面还添加了,ROM,用来存取IIC的常数和读来的数据。
i2c-bus_verilog
- i2c总线的CPLD程序,是用verilog语言编写的,直接添加进去就可以用了。
i2c_slave
- 在一个32单元CPLD中实现的I2C SLave device-Minimal I2C Slave Device in a 32cell PLD
MYFX2
- usb cy7c68013开发板中CPLD的源代码-USB2.0-128P to restore the I2C settings dev_io
I2C
- I2C core code in Hardware descrption language so as enable a cpld/fpga to be programmed for specific customized applications of our requirment & make the pcb work to meet the application requirements.
i2c
- IIC 接口EEPROM 存取实验(verilog实现) 按动开发板键盘某个键 CPLD 将拨码开关的数据写入EEPROM 的某个地址,按动另 外一个键,将刚写入的数据读回CPLD,并在数码管上显示。帮助读者掌握I2C 的总线协 议和EEPROM 的读写方法。-verilog
I2Cslave1
- I2C slave for FPGA and CPLD.
i2c
- CIwei CPLD开发使用VHDL 编写的II2的应用实例-CIwei CPLD using VHDL prepared to develop the application of II2
i2c
- 单片机和cpld通信中单片机c语言的原程序代码-Single-chip and single-chip communication cpld the original c language code
I2C-CPLD
- I2C总线通讯的CPLD实现,包括详细的设计方法及源程序。-I2C总线通讯的CPLD实现
i2c
- 按动开发板键盘某个键CPLD将拨码开关的数据写入EEPROM的某个地址,按动另外一个键,将刚写入的数据 -- 读回CPLD,并在数码管上显-Pressing a button keyboard CPLD development board DIP switches, the data will be written to EEPROM in an address, pressing another key, the newly written data- read back CPLD, an
cpld_I2C
- CPLD+ARM的I2C通信,cpld上的I2C接收程序,内含仿真测试程序-I2C slave for cpld and ARM
cpld-I2C--vhdl
- 此源码为cpld 的 I2c 总线设计的VHDL语言-The source code for the cpld of the VHDL language I2c bus design
CPLD1270-I2C
- I2C总线是一种非常常用的串行总线,它操作简便,占用接口少。本程序介绍操作一个I2C总线接口的EEPROM AT24C02的方法,使用户了解I2C总线协议和读写方法。 实验过程是:按动开发板键盘某个键CPLD将拨码开关的数据写入EEPROM的某个地址,按动另外一个键,将刚写入的数据读回CPLD,并在数码管上显示。(sw0为写入,sw1为读出)-I2C bus is a very popular serial bus, it is simple, taking less interface.
I2C
- 基于CPLD的I2C总线程序,采用EM570与24C01实现通讯!-EM570 and 24C01, for CPLD
i2c-eeprom
- I2C 与EEPROM之间数据的传输和存储,使用在CPLD上,通过键盘输入数据,在数码管上进行显示并存储在EEPROM中-the read and write between i2c and eeprom
I2C
- fpga cpld verilog hdl 语言 代码程序 beep 控制
I2Csalve.v
- Modified I2C salve design 1. Asynchronous design: ASIC or FPGA design option 2. 8 bits CSR RW interface: 0~15, address and control 3. PAD not included 4. Altera CPLD verified