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xuliejiasnceqi
- 序列检测器,用MAXPLUS2设计的,我自己的设计成果,提供给那些刚对数字设计入门的新手们-Sequence detector, using MAXPLUS2 design, design my own results to those just getting started on the digital design novices
qiangdaqi
- 筛选抢答成功者,用于抢答比赛中,不是很复杂,呵呵呵呵额-maxplus2
MaxPlus2_novice_learning_manuals
- MaxPlus2新手学习手册:学习软件的必备教程,很详细!-MaxPlus2 novice learning handbook: the essential learning software tutorial, very detailed!
MAXplusII
- maxplus2 功能图标 是你更清楚更加熟悉的使用maxplus2-maxplus2
MAXplusII_(VHDL)
- 用maxplus2和vhdl 实现重要典型电路设计 是你的首选 -maxplus2
MAXplusII_
- maxplus2 的功能达介绍 让你更加 熟练使用这个软件 更加清晰-maxplus2
3
- 】文章介绍了用于体育比赛的数字秒表的VHDL 设计, 并基于FPGA 在MAXPLUS2 软件下, 采用ALTRA 公司FLEX10K 系列的EPF10K10LC84- 4 芯片进行了计算机仿真-】 This article introduces digital stopwatch for sports competition in the VHDL design and FPGA-based software in MAXPLUS2, using ALTRA company FLEX10K
mclock
- 用VHDL编写的带闹钟报时功能的数字钟 ,现代数字系统设计作业。 采用文本图形混合输入,在maxplus2 10.0运行通过-Written by VHDL figures with alarm chime clock, modern digital system design work. Graphics mixed with text input, run by the maxplus2 10.0
2to10
- 2 to 10 bcd under vhdl langage in maxplus2 good one
multiply
- 实验报告中完成以下功能:在maxplus2 环境下,完成4bit × 4bit 运算功能,并模拟显示出相关内容,设计动态扫描显示电路,显示两位字符,以便用在4bit × 4bit运算中。 (附源程序代码)-multiplay under maxplus2,use VHDL
vote7_plus
- 七人表决器完整工程项目,VHDL语言编写,Maxplus2环境,内有仿真图,实验可用-Seven voting integrity project, VHDL language, Maxplus2 environment, there are simulation diagram, experimental available ~ ~
stop_watch
- stopwatch source it is maded by maxplus2
commond
- Maxplus2软件最常用到的命令,能够帮助很好的了解软件开发环境-Maxplus2 most commonly used software commands, can help a good understanding of software development environment
license
- Maxplus2软件在安装过程中不可缺少的文件-Maxplus2 software is indispensable during the installation file
clock
- EDA用maxplus2开发设计的简易数字钟,适合初学者,vhdL语言-EDA maxplus2 in development and design of simple digital clock, is suitable for beginners, vhdL language
four_bit-data-selector
- 四位的数据选择器,可在maxplus2上运行并仿真-Four of the data selection, which can be run on the maxplus2 and Simulation
APDLL
- 数字锁相环的FPGA设计与实现,用maxplus2实现的-DPLL FPGA design and implementation, with maxplus2 achieve
clock
- 时钟,用maxplus2做的,可以重置时间,可以设置闹铃。-The clock, with maxplus2 do,it can reset the time and set the alarm.
Tpinng_panngh
- 这是用AHDL语言开发的一个PCI采集系统的逻辑源码,其中的乒乓设计思思路新颖,有兴趣的朋友能参考一下!编译环境为maxplus2 可直接使用。 -AHDL language developed a PCI acquisition system logic source code, which the novel ping-pong the design Chaosisi Road, friends who are interested can refer to! Compilation e
DT
- 基于maxplus2的心跳记录器设计,可以显示,回放,报警-failed to translate